Chinmay Deshpande ca7edf2d14

[AMDGPU][GISel] Add RegBankLegalize support for G_STRICT_{FADD|FMUL} (#169406)

2025-12-02 06:55:25 -08:00

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AArch64

[AArch64] Improve select dagcombine (#169925)

2025-12-02 12:29:49 +00:00

AMDGPU

[AMDGPU][GISel] Add RegBankLegalize support for G_STRICT_{FADD|FMUL} (#169406)

2025-12-02 06:55:25 -08:00

ARC

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ARM

Avoid maxnum(sNaN, x) optimizations / folds (#170181)

2025-12-02 12:43:03 +00:00

AVR

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BPF

Revert "[BPF] Allow libcalls behind a feature gate (#168442)" (#169733)

2025-12-01 11:19:39 -08:00

CSKY

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DirectX

[NFC] [DirectX] Make DirectX codegen test CBufferAccess/gep-ce-two-uses.ll more strict (#169855)

2025-11-27 13:58:47 -08:00

Generic

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Hexagon

Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)" (#169219)

2025-11-24 09:27:25 +08:00

Inputs

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Lanai

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LoongArch

[LoongArch] Make rotl/rotr custom for lsx/lasx (#161154)

2025-11-28 15:28:19 +08:00

M68k

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Mips

[Mips] Set custom lowering for STRICT_FSETCC/STRICT_FSETCCS ops. (#168303)

2025-11-25 00:02:37 -05:00

MIR

Add IR and codegen support for deactivation symbols.

2025-11-26 12:37:09 -08:00

MIR2Vec

[AMX][NFC] Organize tilerow (#168193)

2025-11-28 15:02:47 +08:00

MLRegAlloc

[MLGO] Remove Extra Dev Mode Features (#167273)

2025-11-10 08:40:28 -08:00

MSP430

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NVPTX

[NVPTX] Fix lit test issues from masked load/store implementation (#169535)

2025-11-25 12:27:31 -06:00

PowerPC

[PowerPC ]convert (setcc (and X, 1), 0, eq) to XORI (and X, 1), 1 (#168384)

2025-11-25 13:16:39 -05:00

RISCV

[NFC][RISCV] Correct fminimumnum test case (#170169)

2025-12-02 09:35:11 +08:00

SPARC

[SPARC] Properly handle CC for long double on sparc32 (#162226)

2025-11-29 21:30:39 +07:00

SPIRV

[HLSL][SPIR-V] Add support for SV_Target semantic (#168743)

2025-12-02 13:19:00 +00:00

SystemZ

[SystemZ] Serialize ada entry flags (#169395)

2025-11-27 08:14:43 -05:00

Thumb

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Thumb2

[ARM] Add tests for over-sized mulh. NFC

2025-12-02 10:46:39 +00:00

VE

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WebAssembly

[WebAssembly] Optimize away mask of 63 for shl ( zext (and i32 63))) (#152397)

2025-12-01 11:32:46 +00:00

WinCFGuard

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WinEH

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X86

[X86] combineConcatVectorOps - add handling to concat setcc instructions together (#170295)

2025-12-02 14:50:51 +00:00

XCore

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Xtensa

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