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llvm-project/llvm/lib/Target/RISCV
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Sudharsan Veeravalli 60f3fdde88
[RISCV][Outliner] Use MCRegister. NFC (#128291)
2025-02-22 12:46:03 +05:30
..
AsmParser
[RISCV] Move the RISCVII namespaced enums into RISCVVType namespace in RISCVTargetParser.h. NFC (#127585)
2025-02-18 08:27:25 -08:00
Disassembler
[RISCV] Assembler support for XRivosVizip (#127694)
2025-02-21 15:44:33 -08:00
GISel
[RISCV] Move the RISCVII namespaced enums into RISCVVType namespace in RISCVTargetParser.h. NFC (#127585)
2025-02-18 08:27:25 -08:00
MCA
[RISCV] Move the RISCVII namespaced enums into RISCVVType namespace in RISCVTargetParser.h. NFC (#127585)
2025-02-18 08:27:25 -08:00
MCTargetDesc
[RISCV][Outliner] Use MCRegister. NFC (#128291)
2025-02-22 12:46:03 +05:30
TargetInfo
…
CMakeLists.txt
Recommit "[RISCV] Add a pass to remove ADDI by reassociating to fold into load/store address. (#127151)"
2025-02-19 12:11:00 -08:00
RISCV.h
Recommit "[RISCV] Add a pass to remove ADDI by reassociating to fold into load/store address. (#127151)"
2025-02-19 12:11:00 -08:00
RISCV.td
[RISCV] Add a generic OOO CPU (#120712)
2025-02-14 17:35:02 +08:00
RISCVAsmPrinter.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVCallingConv.cpp
[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)
2024-10-01 22:09:27 -07:00
RISCVCallingConv.h
[RISCV] Reduce the interface to RISCVCCAssignFn. NFC (#107503)
2024-09-06 09:28:33 -07:00
RISCVCallingConv.td
[RISCV] Implement getIPRACSRegs hook (#125586)
2025-02-04 10:02:42 -03:00
RISCVCodeGenPrepare.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00
RISCVCombine.td
[GISel] Combine (neg (min/max x, (neg x))) into (max/min x, (neg x)) (#120998)
2025-01-02 16:29:34 -08:00
RISCVConstantPoolValue.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00
RISCVConstantPoolValue.h
[RISCV] Support the large code model. (#70308)
2024-09-09 09:15:07 +08:00
RISCVDeadRegisterDefinitions.cpp
[CodeGen][NewPM] Port LiveStacks analysis to NPM (#118778)
2024-12-06 15:16:07 +05:30
RISCVExpandAtomicPseudoInsts.cpp
…
RISCVExpandPseudoInsts.cpp
[RISCV] Support multiple memory operands in expandRV32ZdinxStore.
2025-01-27 22:10:51 -08:00
RISCVFeatures.td
[RISCV] Assembler support for XRivosVizip (#127694)
2025-02-21 15:44:33 -08:00
RISCVFoldMemOffset.cpp
Recommit "[RISCV] Add a pass to remove ADDI by reassociating to fold into load/store address. (#127151)"
2025-02-19 12:11:00 -08:00
RISCVFrameLowering.cpp
[FrameLowering] Use MCRegister instead of Register in CalleeSavedInfo. NFC (#128095)
2025-02-20 23:44:05 -08:00
RISCVFrameLowering.h
[RISCV] Stack clash protection for dynamic alloca (#122508)
2025-01-16 11:58:42 -08:00
RISCVGatherScatterLowering.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVGISel.td
[RISCV] Move GIComplexOperandMatcher and GICustomOperandRenderer next to their SelectionDAG equivalents. NFC (#119729)
2024-12-12 14:41:57 -08:00
RISCVIndirectBranchTracking.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVInsertReadWriteCSR.cpp
…
RISCVInsertVSETVLI.cpp
[RISCV] Move the RISCVII namespaced enums into RISCVVType namespace in RISCVTargetParser.h. NFC (#127585)
2025-02-18 08:27:25 -08:00
RISCVInsertWriteVXRM.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVInstrFormats.td
[RISCV] Add policy operand to masked vector compare pseudos. Remove ForceTailAgnostic. NFC (#127575)
2025-02-18 07:05:05 -08:00
RISCVInstrFormatsC.td
[RISCV] Add a default assignment of Inst{12-7} to RVInst16CSS. NFC
2025-01-10 14:28:54 -08:00
RISCVInstrFormatsV.td
…
RISCVInstrGISel.td
[RISCV][GISel] Custom promote s32 G_SHL/ASHR/LSHR on RV64. (#115559)
2024-11-11 20:59:21 -08:00
RISCVInstrInfo.cpp
[RISCV][Outliner] Use MCRegister. NFC (#128291)
2025-02-22 12:46:03 +05:30
RISCVInstrInfo.h
[RISCV] Implement isHighLatencyDef() (#127476)
2025-02-18 14:24:20 +08:00
RISCVInstrInfo.td
[RISCV] Assembler support for XRivosVizip (#127694)
2025-02-21 15:44:33 -08:00
RISCVInstrInfoA.td
[RISCV] Remove unnecessary patterns from RISCVInstrInfoA.td. NFC
2024-12-17 10:24:50 -08:00
RISCVInstrInfoC.td
[RISCV] Add a default assignment of Inst{12-7} to RVInst16CSS. NFC
2025-01-10 14:28:54 -08:00
RISCVInstrInfoD.td
[RISCV][GISel] Support G_MERGE_VALUES/G_UNMERGE_VALUES with Zfa. (#120379)
2025-01-07 07:50:50 -08:00
RISCVInstrInfoF.td
[RISCV][GISel] Add register class to some isel output patterns so they can be imported.
2024-11-24 19:29:52 -08:00
RISCVInstrInfoM.td
…
RISCVInstrInfoSFB.td
[RISCV] Add OperandType for condition code arguments used by select and SFB pseudos. (#114163)
2024-10-29 21:23:31 -07:00
RISCVInstrInfoV.td
[RISCV][NFC] Adopt DiagnosticString interface (#126290)
2025-02-08 07:59:55 -08:00
RISCVInstrInfoVPseudos.td
[RISCV] Remove unused VPseudo tablegen class. NFC
2025-02-21 22:10:09 -08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Select mask operands as virtual registers and eliminate uses of vmv0 (#125026)
2025-02-12 12:06:55 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Add policy operand to masked vector compare pseudos. Remove ForceTailAgnostic. NFC (#127575)
2025-02-18 07:05:05 -08:00
RISCVInstrInfoXCV.td
[RISCV][NFC] Adopt DiagnosticString interface (#126290)
2025-02-08 07:59:55 -08:00
RISCVInstrInfoXMips.td
[RISCV] Simplify MIPS CCMov patterns. NFC (#125318)
2025-02-01 09:36:31 -08:00
RISCVInstrInfoXqci.td
[RISCV] Renaming muladdi to muliadd as per v0.5 spec. (#124237)
2025-01-27 20:40:45 -08:00
RISCVInstrInfoXRivos.td
[RISCV] Assembler support for XRivosVizip (#127694)
2025-02-21 15:44:33 -08:00
RISCVInstrInfoXSf.td
[RISCV] Add @earlyclobber to SiFive custom matrix multiply instruction. (#124060)
2025-01-23 08:26:39 -08:00
RISCVInstrInfoXTHead.td
[RISCV] Swap rs1 and rs2 names in TH_ADDSL patterns. NFC
2024-12-29 12:44:33 -08:00
RISCVInstrInfoXVentana.td
…
RISCVInstrInfoXwch.td
[RISCV][NFCI] Rationalize Immediate Definitions (#120718)
2024-12-21 09:47:07 +00:00
RISCVInstrInfoZa.td
…
RISCVInstrInfoZalasr.td
[RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (#82914)
2024-12-17 00:19:45 -08:00
RISCVInstrInfoZb.td
[RISCV] Support Zb*/P Shared Instructions (#127160)
2025-02-15 22:26:02 +08:00
RISCVInstrInfoZc.td
[RISCV][NFC] Adopt DiagnosticString interface (#126290)
2025-02-08 07:59:55 -08:00
RISCVInstrInfoZcmop.td
…
RISCVInstrInfoZfa.td
[RISCV][NFC] Adopt DiagnosticString interface (#126290)
2025-02-08 07:59:55 -08:00
RISCVInstrInfoZfbfmin.td
[RISCV] Remove RISCVISD::FP_ROUND_BF16.
2024-09-03 20:18:01 -07:00
RISCVInstrInfoZfh.td
[RISCV][GISel] Add register class to some isel output patterns so they can be imported.
2024-11-24 19:29:52 -08:00
RISCVInstrInfoZicbo.td
…
RISCVInstrInfoZicfiss.td
…
RISCVInstrInfoZicond.td
…
RISCVInstrInfoZimop.td
…
RISCVInstrInfoZk.td
[RISCV] Combine RVBUnary and RVKUnary into classes that are more similar to ALU(W)_r(r/i). NFC (#111279)
2024-10-06 11:47:30 -07:00
RISCVInstrInfoZvfbf.td
[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945)
2024-09-05 15:27:48 +08:00
RISCVInstrInfoZvk.td
[RISCV] Select mask operands as virtual registers and eliminate uses of vmv0 (#125026)
2025-02-12 12:06:55 +08:00
RISCVISelDAGToDAG.cpp
[RISCV] Move the RISCVII namespaced enums into RISCVVType namespace in RISCVTargetParser.h. NFC (#127585)
2025-02-18 08:27:25 -08:00
RISCVISelDAGToDAG.h
[RISCV] Include RISCVGenSearchTable.inc in RISCVISelDAGToDAG.h (#126326)
2025-02-07 17:13:56 -08:00
RISCVISelLowering.cpp
[RISCV] Remove now redundant isElementRotate shuffle lowering [NFCI] (#128064)
2025-02-21 09:17:56 -08:00
RISCVISelLowering.h
[RISCV] Move the RISCVII namespaced enums into RISCVVType namespace in RISCVTargetParser.h. NFC (#127585)
2025-02-18 08:27:25 -08:00
RISCVLandingPadSetup.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00
RISCVMachineFunctionInfo.cpp
[RISCV] Add stack clash protection (#117612)
2024-12-10 16:48:26 +00:00
RISCVMachineFunctionInfo.h
[RISCV] Stack clash protection for dynamic alloca (#122508)
2025-01-16 11:58:42 -08:00
RISCVMacroFusion.td
…
RISCVMakeCompressible.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVMergeBaseOffset.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVMoveMerger.cpp
…
RISCVOptWInstrs.cpp
[RISCV] Add PseudoCCMOVGPRNoX0 to RISCVOptWInstrs.
2025-01-31 15:09:11 -08:00
RISCVPfmCounters.td
[RISCV][llvm-exegesis] Add default Pfm cycle counter. (#121866)
2025-01-07 09:51:34 -08:00
RISCVPostRAExpandPseudoInsts.cpp
[RISCV] Correct the pass name for RISCVPostRAExpandPseudo.
2024-12-05 16:43:30 -08:00
RISCVProcessors.td
[RISCV] Add a generic OOO CPU (#120712)
2025-02-14 17:35:02 +08:00
RISCVProfiles.td
[RISCV] Use the 'B' extension in RISC-V profile definitions (#113942)
2024-11-10 07:18:05 +00:00
RISCVPushPopOptimizer.cpp
…
RISCVRedundantCopyElimination.cpp
…
RISCVRegisterInfo.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVRegisterInfo.h
[RISCV] Move the RISCVII namespaced enums into RISCVVType namespace in RISCVTargetParser.h. NFC (#127585)
2025-02-18 08:27:25 -08:00
RISCVRegisterInfo.td
[RISCV] Improve Errors for GPRNoX0 Reg Class (#126397)
2025-02-10 17:21:51 -08:00
RISCVSchedGenericOOO.td
[RISCV] Add a generic OOO CPU (#120712)
2025-02-14 17:35:02 +08:00
RISCVSchedMIPSP8700.td
[RISCV] Remove duplicate WriteRes<WriteJalr for MIPSP8700. (#123865)
2025-01-22 10:37:01 -08:00
RISCVSchedRocket.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSchedSiFive7.td
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVSchedSiFiveP400.td
[RISCV] Update the latencies of MUL and CPOP in SiFive P400 scheduling model (#122007)
2025-01-07 15:01:05 -08:00
RISCVSchedSiFiveP500.td
[RISCV] Add P550 scheduler model. (#124639)
2025-01-27 22:40:05 -08:00
RISCVSchedSiFiveP600.td
[RISCV] Fix the worst case for VSHA2MS in SiFive P400/P600 scheduling models (#116893)
2024-11-21 10:59:46 -08:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Remove some unnecessary UnsupportedSched* that are implied by others. NFC
2025-01-21 18:00:52 -08:00
RISCVSchedSyntacoreSCR7.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSchedSyntacoreSCR345.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSchedTTAscalonD8.td
[RISC-V] Base scheduling model for tt-ascalon-d8 (#120160)
2024-12-20 15:30:17 -05:00
RISCVSchedule.td
[RISCV] Add missing ReadFMA16Addend in UnsupportedSchedZfh
2024-12-31 17:22:08 +08:00
RISCVScheduleV.td
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVScheduleXSf.td
…
RISCVScheduleZb.td
…
RISCVScheduleZvk.td
[RISCV] Assign separate PseudoVSHA2MS_VV opcodes for each SEW (#114317)
2024-10-31 10:21:14 -07:00
RISCVSchedXiangShanNanHu.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSelectionDAGInfo.cpp
[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)
2024-12-21 05:29:51 +03:00
RISCVSelectionDAGInfo.h
[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)
2024-12-21 05:29:51 +03:00
RISCVSubtarget.cpp
[RISCV] Add MIPS extensions (#121394)
2025-01-28 08:04:09 +01:00
RISCVSubtarget.h
[RISCV] Fix some implicit conversions from Register to unsigned. NFC
2025-02-05 17:06:10 -08:00
RISCVSystemOperands.td
[RISCV] Support [mh]edelegh CSRs (#121634)
2025-02-16 13:41:46 -08:00
RISCVTargetMachine.cpp
[RISCV] Move VMV0 elimination past machine SSA opts (#126850)
2025-02-20 12:41:05 +08:00
RISCVTargetMachine.h
[CodeGen] Move MISched target hooks into TargetMachine (#125700)
2025-02-05 11:41:37 +05:30
RISCVTargetObjectFile.cpp
[RISCV] Support the large code model. (#70308)
2024-09-09 09:15:07 +08:00
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV] Move the RISCVII namespaced enums into RISCVVType namespace in RISCVTargetParser.h. NFC (#127585)
2025-02-18 08:27:25 -08:00
RISCVTargetTransformInfo.h
[TTI][CostModel] Add cost modeling for expandload and compressstore intrinsics (#122882)
2025-02-04 15:08:30 +03:00
RISCVVectorMaskDAGMutation.cpp
[RISCV] Move the RISCVII namespaced enums into RISCVVType namespace in RISCVTargetParser.h. NFC (#127585)
2025-02-18 08:27:25 -08:00
RISCVVectorPeephole.cpp
[RISCV] Move the RISCVII namespaced enums into RISCVVType namespace in RISCVTargetParser.h. NFC (#127585)
2025-02-18 08:27:25 -08:00
RISCVVLOptimizer.cpp
[RISCV][VLOPT] Move mayReadPastVL check into getMinimumVLForUser. NFC (#127972)
2025-02-20 20:17:18 +08:00
RISCVVMV0Elimination.cpp
[RISCV] Move VMV0 elimination past machine SSA opts (#126850)
2025-02-20 12:41:05 +08:00
RISCVZacasABIFix.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00