shylie/llvm-project

History

Durgadoss R 6a075a9d5d

[MLIR][NVVM]: Update setmaxregister NVVM Op (#77594 )

This patch updates the setmaxregister NVVM Op to use the
intrinsics instead of inline-ptx.

* The interface remains same (as expected).
* Tests are added to verify the lowered intrinsics in
Target/LLVMIR/nvvmir.mlir.

Signed-off-by: Durgadoss R <durgadossr@nvidia.com>

2024-01-10 18:49:09 +01:00

..

benchmark/python

[mlir][benchmark] Fix broken benchmark script (#68841 )

2023-12-06 12:17:53 +05:30

Revert "[mlir] Consider mlir-linalg-ods-gen as a tablegen tool in build (#75093 )"

2024-01-04 02:01:16 +05:00

[acc] Fix OpenACC documentation (#77502 )

2024-01-09 11:12:41 -08:00

[mlir] add a chapter on matchers to the transform dialect tutorial (#76725 )

2024-01-09 13:19:41 +01:00

[MLIR][NVVM]: Update setmaxregister NVVM Op (#77594 )

2024-01-10 18:49:09 +01:00

[mlir] allow inlining complex ops (#77514 )

2024-01-10 09:23:36 -08:00

[mlir][python] add MemRefTypeAttr attr builder (#76371 )

2024-01-06 16:42:14 -06:00

[MLIR][NVVM]: Update setmaxregister NVVM Op (#77594 )

2024-01-10 18:49:09 +01:00

[mlir][mesh] Add lowering of process multi-index op (#77490 )

2024-01-10 07:01:16 -08:00

[mlir][openacc] Restore unit tests for device_type functions (#77122 )

2024-01-09 09:51:05 -08:00

[emacs] Fix Emacs library formatting (#76110 )

2024-01-10 13:14:21 +01:00

.clang-format

…

.clang-tidy

…

CMakeLists.txt

[mlir] Add config for PDL (#69927 )

2024-01-03 20:37:20 -08:00

LICENSE.TXT

…

README.md

…

README.md

Multi-Level Intermediate Representation

See https://mlir.llvm.org/ for more information.