Dmitry Sidorov d2dab9788a

[SPIR-V] Decompose bitcasts involving bool vectors (#187960) ...

OpTypeBool has no defined bitwidth in SPIR-V, so OpBitcast is invalid
for boolean vector types. Decompose `<N x i1> <-> iN` bitcasts into
element-wise extract/shift/OR and AND/icmp/insert sequences during IR
preprocessing.

Fixes:
https://github.com/kuhar/iree/blob/amdgcn-spirv/spirv-repros/bitcast_crash.ll
and https://github.com/llvm/llvm-project/issues/185815

2026-03-24 23:58:07 +01:00

..

AArch64

Revert "[GlobalISel][LLT] Introduce FPInfo for LLT (Enable bfloat, ppc128float and others in GlobalISel) (#155107)" (#188344)

2026-03-24 21:40:36 +00:00

AMDGPU

[SelectionDAG] Add known bit for ISD::FABS (#188335)

2026-03-24 14:53:06 -06:00

ARC

…

ARM

[DAG] ComputeKnownBits - set low bit to zero for ADD(X,X) (#186461)

2026-03-23 16:10:36 +00:00

AVR

[AVR] Improve expansion of pseudo instruction SPREAD (#186780)

2026-03-16 21:24:20 +01:00

BPF

[BPF] Use ".L" local prefix label for basic blocks (#95103)

2026-03-15 19:28:00 +01:00

CSKY

…

DirectX

[HLSL] Add WaveActiveBitAnd builtin function (#187149)

2026-03-23 10:19:18 -07:00

Generic

…

Hexagon

[Hexagon] Optimize load/store instruction during widening (#186962)

2026-03-24 11:41:24 +05:30

Inputs

…

Lanai

…

LoongArch

[TargetLowering] In BuildSDIV, avoid creating build_vector with illegal scalar types after type legalization. (#188280)

2026-03-24 12:27:10 -07:00

M68k

[M68k] Fix pipeline.ll test after CodeGenPrepare analysis change (#187617)

2026-03-20 09:57:45 +08:00

Mips

[Mips] Add r5900 (PlayStation 2 Emotion Engine) FPU Support (#178942)

2026-03-22 23:48:00 -04:00

MIR

Revert "[GlobalISel][LLT] Introduce FPInfo for LLT (Enable bfloat, ppc128float and others in GlobalISel) (#155107)" (#188344)

2026-03-24 21:40:36 +00:00

MIR2Vec

…

MLRegAlloc

…

MSP430

…

NVPTX

[NVPTX] Fix assumption of sm versioning (#188282)

2026-03-24 10:39:36 -07:00

PowerPC

[DAG] ComputeKnownBits - set low bit to zero for ADD(X,X) (#186461)

2026-03-23 16:10:36 +00:00

RISCV

[RISCV] Use uimm3/4/5/6_plus1 for (P)SATI instructions. (#186541)

2026-03-24 11:48:55 -07:00

SPARC

…

SPIRV

[SPIR-V] Decompose bitcasts involving bool vectors (#187960)

2026-03-24 23:58:07 +01:00

SystemZ

[SystemZ] Remove custom lowering of f16 IS_FPCLASS (#187532)

2026-03-22 17:19:24 +01:00

Thumb

[ARM] Try to lower sign bit SELECT_CC to shift (#186349)

2026-03-16 09:32:43 +01:00

Thumb2

[DAGCombine] Optimize away cond ? 1 : 0 post-legalization (#186771)

2026-03-20 16:23:18 +01:00

VE

[LegalizeTypes] Keep non-negative info in SUB(CTLZ) (#186338)

2026-03-24 09:17:17 +01:00

WebAssembly

Reland "[WebAssembly][FastISel] Fold i64 extension chains into widened loads" (#188324)

2026-03-24 20:12:29 +00:00

WinCFGuard

[CFGuard] Consider function aliases as indirect call targets (#188223)

2026-03-24 18:55:46 +01:00

WinEH

…

X86

[CodeGen][NewPM] Mark ExpandPostRAPseudos as required (#188304)

2026-03-24 13:26:39 -07:00

XCore

…

Xtensa

…