cdfd884b0e
Update TableGen specification of DXIL Op records in DXIL.td per the current design document. - Facilitate specification of overloads, shader stage and attributes predicated on DXIL Ops predicated DXIL version. Implement functionality to consume in TableGen backend, DXILEmitter, the above specification enhancements, and generate C++ code (in (DXILOperations.inc) that represents properties of DXIL Ops, associated type declarations and corresponding accessor functions. Changes to DXIL Op Lowering pass to consume the DXIL Op representation generated by the TableGen back end. Add mtriple with the required shader model version to commandline of tests.
26 lines
974 B
LLVM
26 lines
974 B
LLVM
; RUN: opt -S -dxil-intrinsic-expansion -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s --check-prefixes=CHECK,EXPCHECK
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; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s --check-prefixes=CHECK,DOPCHECK
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; Make sure dxil operation function calls for log10 are generated.
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define noundef float @log10_float(float noundef %a) #0 {
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entry:
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; DOPCHECK: call float @dx.op.unary.f32(i32 23, float %{{.*}})
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; EXPCHECK: call float @llvm.log2.f32(float %a)
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; CHECK: fmul float 0x3FD3441340000000, %{{.*}}
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%elt.log10 = call float @llvm.log10.f32(float %a)
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ret float %elt.log10
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}
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define noundef half @log10_half(half noundef %a) #0 {
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entry:
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; DOPCHECK: call half @dx.op.unary.f16(i32 23, half %{{.*}})
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; EXPCHECK: call half @llvm.log2.f16(half %a)
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; CHECK: fmul half 0xH34D1, %{{.*}}
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%elt.log10 = call half @llvm.log10.f16(half %a)
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ret half %elt.log10
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}
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declare half @llvm.log10.f16(half)
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declare float @llvm.log10.f32(float)
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