
Update TableGen specification of DXIL Op records in DXIL.td per the current design document. - Facilitate specification of overloads, shader stage and attributes predicated on DXIL Ops predicated DXIL version. Implement functionality to consume in TableGen backend, DXILEmitter, the above specification enhancements, and generate C++ code (in (DXILOperations.inc) that represents properties of DXIL Ops, associated type declarations and corresponding accessor functions. Changes to DXIL Op Lowering pass to consume the DXIL Op representation generated by the TableGen back end. Add mtriple with the required shader model version to commandline of tests.
32 lines
990 B
LLVM
32 lines
990 B
LLVM
; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s
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; Make sure dxil operation function calls for umax are generated for i16/i32/i64.
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; CHECK-LABEL:test_umax_i16
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define noundef i16 @test_umax_i16(i16 noundef %a, i16 noundef %b) {
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entry:
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; CHECK: call i16 @dx.op.binary.i16(i32 39, i16 %{{.*}}, i16 %{{.*}})
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%0 = call i16 @llvm.umax.i16(i16 %a, i16 %b)
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ret i16 %0
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}
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; CHECK-LABEL:test_umax_i32
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define noundef i32 @test_umax_i32(i32 noundef %a, i32 noundef %b) {
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entry:
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; CHECK: call i32 @dx.op.binary.i32(i32 39, i32 %{{.*}}, i32 %{{.*}})
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%0 = call i32 @llvm.umax.i32(i32 %a, i32 %b)
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ret i32 %0
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}
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; CHECK-LABEL:test_umax_i64
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define noundef i64 @test_umax_i64(i64 noundef %a, i64 noundef %b) {
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entry:
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; CHECK: call i64 @dx.op.binary.i64(i32 39, i64 %{{.*}}, i64 %{{.*}})
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%0 = call i64 @llvm.umax.i64(i64 %a, i64 %b)
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ret i64 %0
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}
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declare i16 @llvm.umax.i16(i16, i16)
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declare i32 @llvm.umax.i32(i32, i32)
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declare i64 @llvm.umax.i64(i64, i64)
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