53c37f300d
On PowerPC there are 128 bit VSX registers. These registers are half overlapped with 64 bit floating point registers (FPR). The 64 bit half of the VXS register that does not overlap with the FPR does not overlap with any other register class. The FPR are the only subregisters of the VSX registers but they do not fully cover the 128 bit super register. This leads to incorrect lane masks being created. This patch adds phony registers for the other half of the VSX registers in order to fully cover them and to make sure that the lane masks are not the same for the VSX and the floating point register.
28 lines
1.2 KiB
LLVM
28 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown | FileCheck %s
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; Infinite loop identified in D62963.
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define <4 x double> @fneg_fdiv_splat(double %a0, <4 x double> %a1) {
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; CHECK-LABEL: fneg_fdiv_splat:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha
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; CHECK-NEXT: xxspltd 0, 1, 0
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; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l
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; CHECK-NEXT: xvredp 1, 0
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; CHECK-NEXT: lxvd2x 2, 0, 3
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; CHECK-NEXT: xxlor 3, 2, 2
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; CHECK-NEXT: xvmaddadp 3, 0, 1
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; CHECK-NEXT: xvnmsubadp 1, 1, 3
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; CHECK-NEXT: xvmaddadp 2, 0, 1
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; CHECK-NEXT: xvmsubadp 1, 1, 2
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; CHECK-NEXT: xvmuldp 34, 34, 1
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; CHECK-NEXT: xvmuldp 35, 35, 1
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; CHECK-NEXT: blr
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entry:
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%splat.splatinsert = insertelement <4 x double> undef, double %a0, i32 0
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%splat.splat = shufflevector <4 x double> %splat.splatinsert, <4 x double> undef, <4 x i32> zeroinitializer
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%div = fdiv contract reassoc nsz arcp ninf <4 x double> %a1, %splat.splat
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%sub = fsub contract reassoc nsz <4 x double> <double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, %div
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ret <4 x double> %sub
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}
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