53c37f300d
On PowerPC there are 128 bit VSX registers. These registers are half overlapped with 64 bit floating point registers (FPR). The 64 bit half of the VXS register that does not overlap with the FPR does not overlap with any other register class. The FPR are the only subregisters of the VSX registers but they do not fully cover the 128 bit super register. This leads to incorrect lane masks being created. This patch adds phony registers for the other half of the VSX registers in order to fully cover them and to make sure that the lane masks are not the same for the VSX and the floating point register.
201 lines
6.7 KiB
LLVM
201 lines
6.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
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define float @ldexp_f32(i8 zeroext %x) {
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; CHECK-LABEL: ldexp_f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -32(r1)
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; CHECK-NEXT: std r0, 48(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: vspltisw v2, 1
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; CHECK-NEXT: mr r4, r3
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; CHECK-NEXT: xvcvsxwdp vs1, v2
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; CHECK-NEXT: bl ldexpf
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r1, r1, 32
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%zext = zext i8 %x to i32
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%ldexp = call float @llvm.ldexp.f32.i32(float 1.000000e+00, i32 %zext)
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ret float %ldexp
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}
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define double @ldexp_f64(i8 zeroext %x) {
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; CHECK-LABEL: ldexp_f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -32(r1)
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; CHECK-NEXT: std r0, 48(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: vspltisw v2, 1
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; CHECK-NEXT: mr r4, r3
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; CHECK-NEXT: xvcvsxwdp vs1, v2
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; CHECK-NEXT: bl ldexp
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r1, r1, 32
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%zext = zext i8 %x to i32
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%ldexp = call double @llvm.ldexp.f64.i32(double 1.000000e+00, i32 %zext)
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ret double %ldexp
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}
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define <2 x float> @ldexp_v2f32(<2 x float> %val, <2 x i32> %exp) {
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; CHECK-LABEL: ldexp_v2f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -80(r1)
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; CHECK-NEXT: std r0, 96(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 80
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: .cfi_offset v29, -48
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; CHECK-NEXT: .cfi_offset v30, -32
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; CHECK-NEXT: .cfi_offset v31, -16
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; CHECK-NEXT: xxsldwi vs0, v2, v2, 3
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; CHECK-NEXT: li r3, 0
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; CHECK-NEXT: stxv v29, 32(r1) # 16-byte Folded Spill
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; CHECK-NEXT: xscvspdpn f1, vs0
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; CHECK-NEXT: vextuwrx r4, r3, v3
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; CHECK-NEXT: stxv v30, 48(r1) # 16-byte Folded Spill
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; CHECK-NEXT: stxv v31, 64(r1) # 16-byte Folded Spill
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; CHECK-NEXT: vmr v31, v3
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; CHECK-NEXT: vmr v30, v2
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; CHECK-NEXT: bl ldexpf
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; CHECK-NEXT: nop
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; CHECK-NEXT: xxswapd vs0, v30
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; CHECK-NEXT: li r3, 4
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; CHECK-NEXT: xscvdpspn v29, f1
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; CHECK-NEXT: xscvspdpn f1, vs0
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; CHECK-NEXT: vextuwrx r4, r3, v31
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; CHECK-NEXT: bl ldexpf
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; CHECK-NEXT: nop
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; CHECK-NEXT: xscvdpspn vs0, f1
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; CHECK-NEXT: lxv v31, 64(r1) # 16-byte Folded Reload
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; CHECK-NEXT: lxv v30, 48(r1) # 16-byte Folded Reload
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; CHECK-NEXT: xxmrghw v2, vs0, v29
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; CHECK-NEXT: lxv v29, 32(r1) # 16-byte Folded Reload
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; CHECK-NEXT: addi r1, r1, 80
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%1 = call <2 x float> @llvm.ldexp.v2f32.v2i32(<2 x float> %val, <2 x i32> %exp)
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ret <2 x float> %1
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}
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define <4 x float> @ldexp_v4f32(<4 x float> %val, <4 x i32> %exp) {
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; CHECK-LABEL: ldexp_v4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -96(r1)
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; CHECK-NEXT: std r0, 112(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 96
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: .cfi_offset v28, -64
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; CHECK-NEXT: .cfi_offset v29, -48
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; CHECK-NEXT: .cfi_offset v30, -32
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; CHECK-NEXT: .cfi_offset v31, -16
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; CHECK-NEXT: li r3, 12
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; CHECK-NEXT: xscvspdpn f1, v2
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; CHECK-NEXT: stxv v28, 32(r1) # 16-byte Folded Spill
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; CHECK-NEXT: stxv v29, 48(r1) # 16-byte Folded Spill
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; CHECK-NEXT: stxv v30, 64(r1) # 16-byte Folded Spill
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; CHECK-NEXT: stxv v31, 80(r1) # 16-byte Folded Spill
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; CHECK-NEXT: vmr v31, v3
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; CHECK-NEXT: vmr v30, v2
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; CHECK-NEXT: vextuwrx r4, r3, v3
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; CHECK-NEXT: bl ldexpf
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; CHECK-NEXT: nop
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; CHECK-NEXT: xxswapd vs0, v30
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; CHECK-NEXT: li r3, 4
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; CHECK-NEXT: xscpsgndp v29, f1, f1
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; CHECK-NEXT: xscvspdpn f1, vs0
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; CHECK-NEXT: vextuwrx r4, r3, v31
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; CHECK-NEXT: bl ldexpf
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; CHECK-NEXT: nop
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; CHECK-NEXT: xxmrghd vs0, v29, vs1
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; CHECK-NEXT: li r3, 0
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; CHECK-NEXT: vextuwrx r4, r3, v31
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; CHECK-NEXT: xvcvdpsp v28, vs0
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; CHECK-NEXT: xxsldwi vs0, v30, v30, 3
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; CHECK-NEXT: xscvspdpn f1, vs0
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; CHECK-NEXT: bl ldexpf
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; CHECK-NEXT: nop
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; CHECK-NEXT: xxsldwi vs0, v30, v30, 1
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; CHECK-NEXT: xscpsgndp v29, f1, f1
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; CHECK-NEXT: mfvsrwz r4, v31
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; CHECK-NEXT: xscvspdpn f1, vs0
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; CHECK-NEXT: bl ldexpf
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; CHECK-NEXT: nop
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; CHECK-NEXT: xxmrghd vs0, vs1, v29
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; CHECK-NEXT: lxv v31, 80(r1) # 16-byte Folded Reload
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; CHECK-NEXT: lxv v30, 64(r1) # 16-byte Folded Reload
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; CHECK-NEXT: lxv v29, 48(r1) # 16-byte Folded Reload
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; CHECK-NEXT: xvcvdpsp v2, vs0
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; CHECK-NEXT: vmrgew v2, v28, v2
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; CHECK-NEXT: lxv v28, 32(r1) # 16-byte Folded Reload
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; CHECK-NEXT: addi r1, r1, 96
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%1 = call <4 x float> @llvm.ldexp.v4f32.v4i32(<4 x float> %val, <4 x i32> %exp)
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ret <4 x float> %1
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}
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define half @ldexp_f16(half %arg0, i32 %arg1) {
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; CHECK-LABEL: ldexp_f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -32(r1)
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; CHECK-NEXT: std r0, 48(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: xscvdphp f0, f1
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; CHECK-NEXT: clrldi r4, r4, 32
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; CHECK-NEXT: mffprwz r3, f0
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; CHECK-NEXT: clrlwi r3, r3, 16
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: xscvhpdp f1, f0
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; CHECK-NEXT: bl ldexpf
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r1, r1, 32
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%ldexp = call half @llvm.ldexp.f16.i32(half %arg0, i32 %arg1)
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ret half %ldexp
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}
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define ppc_fp128 @ldexp_fp128(ppc_fp128 %arg0, i32 %arg1) {
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; CHECK-LABEL: ldexp_fp128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -32(r1)
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; CHECK-NEXT: std r0, 48(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: clrldi r5, r5, 32
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; CHECK-NEXT: bl ldexpl
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r1, r1, 32
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%ldexp = call ppc_fp128 @llvm.ldexp.ppcf128.i32(ppc_fp128 %arg0, i32 %arg1)
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ret ppc_fp128 %ldexp
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}
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declare double @llvm.ldexp.f64.i32(double, i32) #0
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declare float @llvm.ldexp.f32.i32(float, i32) #0
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declare <2 x float> @llvm.ldexp.v2f32.v2i32(<2 x float>, <2 x i32>) #0
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declare <4 x float> @llvm.ldexp.v4f32.v4i32(<4 x float>, <4 x i32>) #0
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declare half @llvm.ldexp.f16.i32(half, i32) #0
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declare ppc_fp128 @llvm.ldexp.ppcf128.i32(ppc_fp128, i32) #0
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attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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