003b58f65b
Add an intrinsic which returns the two pieces as multiple return values. Alternatively could introduce a pair of intrinsics to separately return the fractional and exponent parts. AMDGPU has native instructions to return the two halves, but could use some generic legalization and optimization handling. For example, we should be able to handle legalization of f16 on older targets, and for bf16. Additionally antique targets need a hardware workaround which would be better handled in the backend rather than in library code where it is now.
416 lines
14 KiB
LLVM
416 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
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define { half, i32 } @test_frexp_f16_i32(half %a) {
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; CHECK-LABEL: test_frexp_f16_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -48(r1)
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; CHECK-NEXT: std r0, 64(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: xscvdphp f0, f1
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; CHECK-NEXT: addi r4, r1, 44
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; CHECK-NEXT: mffprwz r3, f0
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; CHECK-NEXT: clrlwi r3, r3, 16
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: xscvhpdp f1, f0
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; CHECK-NEXT: bl frexpf
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; CHECK-NEXT: nop
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; CHECK-NEXT: lwz r3, 44(r1)
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; CHECK-NEXT: addi r1, r1, 48
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%result = call { half, i32 } @llvm.frexp.f16.i32(half %a)
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ret { half, i32 } %result
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}
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define half @test_frexp_f16_i32_only_use_fract(half %a) {
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; CHECK-LABEL: test_frexp_f16_i32_only_use_fract:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -48(r1)
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; CHECK-NEXT: std r0, 64(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: xscvdphp f0, f1
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; CHECK-NEXT: addi r4, r1, 44
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; CHECK-NEXT: mffprwz r3, f0
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; CHECK-NEXT: clrlwi r3, r3, 16
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: xscvhpdp f1, f0
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; CHECK-NEXT: bl frexpf
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r1, r1, 48
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%result = call { half, i32 } @llvm.frexp.f16.i32(half %a)
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%result.0 = extractvalue { half, i32 } %result, 0
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ret half %result.0
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}
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define i32 @test_frexp_f16_i32_only_use_exp(half %a) {
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; CHECK-LABEL: test_frexp_f16_i32_only_use_exp:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -48(r1)
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; CHECK-NEXT: std r0, 64(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: xscvdphp f0, f1
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; CHECK-NEXT: addi r4, r1, 44
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; CHECK-NEXT: mffprwz r3, f0
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; CHECK-NEXT: clrlwi r3, r3, 16
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: xscvhpdp f1, f0
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; CHECK-NEXT: bl frexpf
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; CHECK-NEXT: nop
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; CHECK-NEXT: lwz r3, 44(r1)
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; CHECK-NEXT: addi r1, r1, 48
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%result = call { half, i32 } @llvm.frexp.f16.i32(half %a)
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%result.0 = extractvalue { half, i32 } %result, 1
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ret i32 %result.0
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}
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define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) {
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; CHECK-LABEL: test_frexp_v2f16_v2i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: .cfi_def_cfa_offset 80
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: .cfi_offset r29, -40
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; CHECK-NEXT: .cfi_offset r30, -32
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; CHECK-NEXT: .cfi_offset f30, -16
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; CHECK-NEXT: .cfi_offset f31, -8
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; CHECK-NEXT: std r29, -40(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r30, -32(r1) # 8-byte Folded Spill
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; CHECK-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill
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; CHECK-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill
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; CHECK-NEXT: stdu r1, -80(r1)
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; CHECK-NEXT: std r0, 96(r1)
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; CHECK-NEXT: xscvdphp f0, f2
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; CHECK-NEXT: addi r30, r1, 32
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; CHECK-NEXT: mr r4, r30
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; CHECK-NEXT: mffprwz r3, f0
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; CHECK-NEXT: clrlwi r3, r3, 16
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: xscvhpdp f31, f0
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; CHECK-NEXT: xscvdphp f0, f1
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; CHECK-NEXT: mffprwz r3, f0
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; CHECK-NEXT: clrlwi r3, r3, 16
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: xscvhpdp f1, f0
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; CHECK-NEXT: bl frexpf
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r29, r1, 36
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; CHECK-NEXT: fmr f30, f1
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; CHECK-NEXT: fmr f1, f31
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; CHECK-NEXT: mr r4, r29
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; CHECK-NEXT: bl frexpf
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; CHECK-NEXT: nop
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; CHECK-NEXT: fmr f2, f1
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; CHECK-NEXT: lfiwzx f0, 0, r30
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; CHECK-NEXT: lfiwzx f1, 0, r29
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; CHECK-NEXT: xxmrghw v2, vs1, vs0
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; CHECK-NEXT: fmr f1, f30
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; CHECK-NEXT: addi r1, r1, 80
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload
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; CHECK-NEXT: lfd f30, -16(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r30, -32(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r29, -40(r1) # 8-byte Folded Reload
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%result = call { <2 x half>, <2 x i32> } @llvm.frexp.v2f16.v2i32(<2 x half> %a)
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ret { <2 x half>, <2 x i32> } %result
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}
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define <2 x half> @test_frexp_v2f16_v2i32_only_use_fract(<2 x half> %a) {
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; CHECK-LABEL: test_frexp_v2f16_v2i32_only_use_fract:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: .cfi_def_cfa_offset 64
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: .cfi_offset f30, -16
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; CHECK-NEXT: .cfi_offset f31, -8
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; CHECK-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill
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; CHECK-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill
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; CHECK-NEXT: stdu r1, -64(r1)
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; CHECK-NEXT: std r0, 80(r1)
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; CHECK-NEXT: xscvdphp f0, f2
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; CHECK-NEXT: addi r4, r1, 40
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; CHECK-NEXT: mffprwz r3, f0
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; CHECK-NEXT: clrlwi r3, r3, 16
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: xscvhpdp f31, f0
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; CHECK-NEXT: xscvdphp f0, f1
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; CHECK-NEXT: mffprwz r3, f0
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; CHECK-NEXT: clrlwi r3, r3, 16
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: xscvhpdp f1, f0
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; CHECK-NEXT: bl frexpf
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r4, r1, 44
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; CHECK-NEXT: fmr f30, f1
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; CHECK-NEXT: fmr f1, f31
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; CHECK-NEXT: bl frexpf
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; CHECK-NEXT: nop
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; CHECK-NEXT: fmr f2, f1
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; CHECK-NEXT: fmr f1, f30
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; CHECK-NEXT: addi r1, r1, 64
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload
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; CHECK-NEXT: lfd f30, -16(r1) # 8-byte Folded Reload
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%result = call { <2 x half>, <2 x i32> } @llvm.frexp.v2f16.v2i32(<2 x half> %a)
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%result.0 = extractvalue { <2 x half>, <2 x i32> } %result, 0
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ret <2 x half> %result.0
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}
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define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) {
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; CHECK-LABEL: test_frexp_v2f16_v2i32_only_use_exp:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: .cfi_def_cfa_offset 80
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: .cfi_offset r29, -32
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; CHECK-NEXT: .cfi_offset r30, -24
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; CHECK-NEXT: .cfi_offset f31, -8
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; CHECK-NEXT: std r29, -32(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r30, -24(r1) # 8-byte Folded Spill
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; CHECK-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill
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; CHECK-NEXT: stdu r1, -80(r1)
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; CHECK-NEXT: std r0, 96(r1)
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; CHECK-NEXT: xscvdphp f0, f2
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; CHECK-NEXT: addi r30, r1, 40
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; CHECK-NEXT: mr r4, r30
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; CHECK-NEXT: mffprwz r3, f0
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; CHECK-NEXT: clrlwi r3, r3, 16
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: xscvhpdp f31, f0
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; CHECK-NEXT: xscvdphp f0, f1
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; CHECK-NEXT: mffprwz r3, f0
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; CHECK-NEXT: clrlwi r3, r3, 16
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: xscvhpdp f1, f0
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; CHECK-NEXT: bl frexpf
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r29, r1, 44
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; CHECK-NEXT: fmr f1, f31
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; CHECK-NEXT: mr r4, r29
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; CHECK-NEXT: bl frexpf
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; CHECK-NEXT: nop
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; CHECK-NEXT: lfiwzx f0, 0, r30
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; CHECK-NEXT: lfiwzx f1, 0, r29
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; CHECK-NEXT: xxmrghw v2, vs1, vs0
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; CHECK-NEXT: addi r1, r1, 80
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r30, -24(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r29, -32(r1) # 8-byte Folded Reload
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%result = call { <2 x half>, <2 x i32> } @llvm.frexp.v2f16.v2i32(<2 x half> %a)
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%result.1 = extractvalue { <2 x half>, <2 x i32> } %result, 1
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ret <2 x i32> %result.1
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}
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define { float, i32 } @test_frexp_f32_i32(float %a) {
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; CHECK-LABEL: test_frexp_f32_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -48(r1)
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; CHECK-NEXT: std r0, 64(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: addi r4, r1, 44
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; CHECK-NEXT: bl frexpf
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; CHECK-NEXT: nop
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; CHECK-NEXT: lwz r3, 44(r1)
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; CHECK-NEXT: addi r1, r1, 48
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%result = call { float, i32 } @llvm.frexp.f32.i32(float %a)
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ret { float, i32 } %result
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}
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define float @test_frexp_f32_i32_only_use_fract(float %a) {
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; CHECK-LABEL: test_frexp_f32_i32_only_use_fract:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -48(r1)
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; CHECK-NEXT: std r0, 64(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: addi r4, r1, 44
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; CHECK-NEXT: bl frexpf
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r1, r1, 48
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%result = call { float, i32 } @llvm.frexp.f32.i32(float %a)
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%result.0 = extractvalue { float, i32 } %result, 0
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ret float %result.0
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}
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define i32 @test_frexp_f32_i32_only_use_exp(float %a) {
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; CHECK-LABEL: test_frexp_f32_i32_only_use_exp:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -48(r1)
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; CHECK-NEXT: std r0, 64(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: addi r4, r1, 44
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; CHECK-NEXT: bl frexpf
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; CHECK-NEXT: nop
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; CHECK-NEXT: lwz r3, 44(r1)
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; CHECK-NEXT: addi r1, r1, 48
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%result = call { float, i32 } @llvm.frexp.f32.i32(float %a)
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%result.0 = extractvalue { float, i32 } %result, 1
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ret i32 %result.0
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}
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; FIXME
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; define { <2 x float>, <2 x i32> } @test_frexp_v2f32_v2i32(<2 x float> %a) {
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; %result = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> %a)
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; ret { <2 x float>, <2 x i32> } %result
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; }
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; define <2 x float> @test_frexp_v2f32_v2i32_only_use_fract(<2 x float> %a) {
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; %result = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> %a)
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; %result.0 = extractvalue { <2 x float>, <2 x i32> } %result, 0
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; ret <2 x float> %result.0
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; }
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; define <2 x i32> @test_frexp_v2f32_v2i32_only_use_exp(<2 x float> %a) {
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; %result = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> %a)
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; %result.1 = extractvalue { <2 x float>, <2 x i32> } %result, 1
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; ret <2 x i32> %result.1
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; }
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define { double, i32 } @test_frexp_f64_i32(double %a) {
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; CHECK-LABEL: test_frexp_f64_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -48(r1)
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; CHECK-NEXT: std r0, 64(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: addi r4, r1, 44
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; CHECK-NEXT: bl frexp
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; CHECK-NEXT: nop
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; CHECK-NEXT: lwz r3, 44(r1)
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; CHECK-NEXT: addi r1, r1, 48
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%result = call { double, i32 } @llvm.frexp.f64.i32(double %a)
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ret { double, i32 } %result
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}
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define double @test_frexp_f64_i32_only_use_fract(double %a) {
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; CHECK-LABEL: test_frexp_f64_i32_only_use_fract:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -48(r1)
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; CHECK-NEXT: std r0, 64(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: addi r4, r1, 44
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; CHECK-NEXT: bl frexp
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r1, r1, 48
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%result = call { double, i32 } @llvm.frexp.f64.i32(double %a)
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%result.0 = extractvalue { double, i32 } %result, 0
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ret double %result.0
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}
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define i32 @test_frexp_f64_i32_only_use_exp(double %a) {
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; CHECK-LABEL: test_frexp_f64_i32_only_use_exp:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -48(r1)
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; CHECK-NEXT: std r0, 64(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: addi r4, r1, 44
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; CHECK-NEXT: bl frexp
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; CHECK-NEXT: nop
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; CHECK-NEXT: lwz r3, 44(r1)
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; CHECK-NEXT: addi r1, r1, 48
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%result = call { double, i32 } @llvm.frexp.f64.i32(double %a)
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%result.0 = extractvalue { double, i32 } %result, 1
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ret i32 %result.0
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}
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; FIXME: Widen vector result
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; define { <2 x double>, <2 x i32> } @test_frexp_v2f64_v2i32(<2 x double> %a) {
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; %result = call { <2 x double>, <2 x i32> } @llvm.frexp.v2f64.v2i32(<2 x double> %a)
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; ret { <2 x double>, <2 x i32> } %result
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; }
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; define <2 x double> @test_frexp_v2f64_v2i32_only_use_fract(<2 x double> %a) {
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; %result = call { <2 x double>, <2 x i32> } @llvm.frexp.v2f64.v2i32(<2 x double> %a)
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; %result.0 = extractvalue { <2 x double>, <2 x i32> } %result, 0
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; ret <2 x double> %result.0
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; }
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; define <2 x i32> @test_frexp_v2f64_v2i32_only_use_exp(<2 x double> %a) {
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; %result = call { <2 x double>, <2 x i32> } @llvm.frexp.v2f64.v2i32(<2 x double> %a)
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; %result.1 = extractvalue { <2 x double>, <2 x i32> } %result, 1
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; ret <2 x i32> %result.1
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; }
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|
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; FIXME: f128 ExpandFloatResult
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; define { ppc_fp128, i32 } @test_frexp_f128_i32(ppc_fp128 %a) {
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; %result = call { ppc_fp128, i32 } @llvm.frexp.f128.i32(ppc_fp128 %a)
|
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; ret { ppc_fp128, i32 } %result
|
|
; }
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|
|
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; define ppc_fp128 @test_frexp_f128_i32_only_use_fract(ppc_fp128 %a) {
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; %result = call { ppc_fp128, i32 } @llvm.frexp.f128.i32(ppc_fp128 %a)
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; %result.0 = extractvalue { ppc_fp128, i32 } %result, 0
|
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; ret ppc_fp128 %result.0
|
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; }
|
|
|
|
; define i32 @test_frexp_f128_i32_only_use_exp(ppc_fp128 %a) {
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; %result = call { ppc_fp128, i32 } @llvm.frexp.f128.i32(ppc_fp128 %a)
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; %result.0 = extractvalue { ppc_fp128, i32 } %result, 1
|
|
; ret i32 %result.0
|
|
; }
|
|
|
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declare { float, i32 } @llvm.frexp.f32.i32(float) #0
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declare { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float>) #0
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|
|
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declare { half, i32 } @llvm.frexp.f16.i32(half) #0
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declare { <2 x half>, <2 x i32> } @llvm.frexp.v2f16.v2i32(<2 x half>) #0
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|
|
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declare { double, i32 } @llvm.frexp.f64.i32(double) #0
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declare { <2 x double>, <2 x i32> } @llvm.frexp.v2f64.v2i32(<2 x double>) #0
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|
|
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declare { half, i16 } @llvm.frexp.f16.i16(half) #0
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declare { <2 x half>, <2 x i16> } @llvm.frexp.v2f16.v2i16(<2 x half>) #0
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|
|
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declare { ppc_fp128, i32 } @llvm.frexp.f128.i32(ppc_fp128) #0
|
|
|
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attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
|