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llvm-project/llvm/test/CodeGen
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Pierre-vh d5eb7ffa33 [Target][ARM] Fold or(A, B) more aggressively for I1 vectors 
This patch makes the folding of or(A, B) into not(and(not(A), not(B)))
more agressive for I1 vector. This only affects Thumb2 MVE and improves
codegen, because it removes a lot of msr/mrs instructions on VPR.P0.

This patch also adds a xor(vcmp) -> !vcmp fold for MVE.

Differential Revision: https://reviews.llvm.org/D77202
2020-05-05 10:03:02 +01:00
..
AArch64
[AArch64] Add NVIDIA Carmel support
2020-05-04 13:52:30 +01:00
AMDGPU
[AMDGPU] fix copies between 32 and 16 bit
2020-05-04 08:54:22 -07:00
ARC
…
ARM
[ARM] Fix tail call validity checking for varargs calls.
2020-05-04 12:34:14 -07:00
AVR
[AVR] Do not place functions in .progmem.data
2020-04-20 13:56:38 +02:00
BPF
BPF: fix a CORE optimization bug
2020-04-20 19:54:51 -07:00
Generic
[MachineDebugify] Insert synthetic DBG_VALUE instructions
2020-04-22 17:03:39 -07:00
Hexagon
[RegisterCoalescer] Extend a subrange if needed when filling range gap
2020-05-04 16:49:59 -05:00
Inputs
…
Lanai
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
Mips
[SelectionDAGBuilder] Stop setting alignment to one for hidden sret values
2020-05-04 14:44:39 +01:00
MIR
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
MSP430
…
NVPTX
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
PowerPC
[PowerPC][AIX][NFC] Remove spills and reloads from arg passing test.
2020-05-04 14:26:33 -04:00
RISCV
[RISCV] Implement convertSelectOfConstantsToMath
2020-05-02 15:05:57 +01:00
SPARC
[Sparc] Fix incorrect operand for matching CMPri pattern
2020-03-02 11:36:32 +08:00
SystemZ
[SystemZ] Fix test case.
2020-04-28 09:43:03 +02:00
Thumb
[ARM] Don't shrink STM if it would cause an unknown base register store
2020-04-22 14:50:42 +01:00
Thumb2
[Target][ARM] Fold or(A, B) more aggressively for I1 vectors
2020-05-05 10:03:02 +01:00
VE
[VE] Update branch instructions
2020-04-28 09:41:01 +02:00
WebAssembly
[SelectionDAGBuilder] Stop setting alignment to one for hidden sret values
2020-05-04 14:44:39 +01:00
WinCFGuard
…
WinEH
…
X86
[x86] add test for shift+op+concat; NFC
2020-05-04 17:31:45 -04:00
XCore
[XCore] Add instruction pattern for bitrev
2020-02-21 09:28:49 +08:00