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llvm-project/llvm/lib/Target/RISCV
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Paul Bowen-Huggett ea06f7f96f
[RISCV] For RV32C, disassembly of c.slli should fail when immediate > 31 (#133713) 
Fixes #133712.

The change causes `c.slli` instructions whose immediate has bit 5 set to
be rejected when disassembling RV32C. Added a test to exhaustively cover
c.slli for 32 bit targets. A minor tweak to make the debug output a
little more readable.

The spec. (20240411) says:

> For RV32C, shamt[5] must be zero; the code points with shamt[5]=1 are
designated for custom extensions. For RV32C and RV64C, the shift amount
must be non-zero; the code points with shamt=0 are HINTs. For all base
ISAs, the code points with rd=x0 are HINTs, except those with shamt[5]=1
in RV32C.
2025-03-31 08:51:34 -07:00
..
AsmParser
[RISCV] Cleanup assembler predicates after #133377. (#133652)
2025-03-30 21:10:08 -07:00
Disassembler
[RISCV] For RV32C, disassembly of c.slli should fail when immediate > 31 (#133713)
2025-03-31 08:51:34 -07:00
GISel
[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)
2025-03-29 11:51:29 +01:00
MCA
Prune a redundant include "RISCVISelDAGToDAG.h" (fixup for #128978)
2025-03-01 14:04:48 +09:00
MCTargetDesc
[RISCV] Remove unused declarations and getSpecifier. NFC
2025-03-30 11:09:56 -07:00
TargetInfo
…
CMakeLists.txt
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
RISCV.h
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
RISCV.td
[RISCV] Add a generic OOO CPU (#120712)
2025-02-14 17:35:02 +08:00
RISCVAsmPrinter.cpp
[RISCV] Rename VariantKind to Specifier
2025-03-20 22:25:57 -07:00
RISCVCallingConv.cpp
[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)
2024-10-01 22:09:27 -07:00
RISCVCallingConv.h
[RISCV] Reduce the interface to RISCVCCAssignFn. NFC (#107503)
2024-09-06 09:28:33 -07:00
RISCVCallingConv.td
[RISCV] Implement getIPRACSRegs hook (#125586)
2025-02-04 10:02:42 -03:00
RISCVCodeGenPrepare.cpp
[RISCV] Vectorize phi for loop carried @llvm.vp.reduce.* (#131974)
2025-03-31 09:13:46 +01:00
RISCVCombine.td
[GISel] Combine (neg (min/max x, (neg x))) into (max/min x, (neg x)) (#120998)
2025-01-02 16:29:34 -08:00
RISCVConstantPoolValue.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00
RISCVConstantPoolValue.h
[RISCV] Support the large code model. (#70308)
2024-09-09 09:15:07 +08:00
RISCVDeadRegisterDefinitions.cpp
[CodeGen][NewPM] Port LiveStacks analysis to NPM (#118778)
2024-12-06 15:16:07 +05:30
RISCVExpandAtomicPseudoInsts.cpp
…
RISCVExpandPseudoInsts.cpp
[RISCV] Use vsetvli instead of vlenb in Prologue/Epilogue (#113756)
2025-03-21 17:22:32 +08:00
RISCVFeatures.td
[RISCV] Add Qualcomm uC Xqciio (External Input Output) extension (#132721)
2025-03-28 19:47:29 -07:00
RISCVFoldMemOffset.cpp
Recommit "[RISCV] Add a pass to remove ADDI by reassociating to fold into load/store address. (#127151)"
2025-02-19 12:11:00 -08:00
RISCVFrameLowering.cpp
[RISCV] Xqciint SystemRegs, Final Assembly Insts (#130867)
2025-03-23 12:04:06 -07:00
RISCVFrameLowering.h
[RISCV] Stack clash protection for dynamic alloca (#122508)
2025-01-16 11:58:42 -08:00
RISCVGatherScatterLowering.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVGISel.td
[RISCV] Move GIComplexOperandMatcher and GICustomOperandRenderer next to their SelectionDAG equivalents. NFC (#119729)
2024-12-12 14:41:57 -08:00
RISCVIndirectBranchTracking.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVInsertReadWriteCSR.cpp
…
RISCVInsertVSETVLI.cpp
[RISCV] Add implicit operand {VL, VTYPE} in RISCVInsertVSETVLI when u… (#130733)
2025-03-13 15:07:07 +08:00
RISCVInsertWriteVXRM.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVInstrFormats.td
[RISCV] Remove Inst bits from Pseudo tablegen class. NFC
2025-02-23 15:08:55 -08:00
RISCVInstrFormatsC.td
[RISCV] Add a default assignment of Inst{12-7} to RVInst16CSS. NFC
2025-01-10 14:28:54 -08:00
RISCVInstrFormatsV.td
[RISCV] Order the implicit defs/uses of vl/vtype on MC instructions the same as the pseudo version. (#129104)
2025-02-27 13:14:22 -08:00
RISCVInstrGISel.td
[RISCV][GISel] Custom promote s32 G_SHL/ASHR/LSHR on RV64. (#115559)
2024-11-11 20:59:21 -08:00
RISCVInstrInfo.cpp
[RISCV] Add shift-add (SH1ADD, ...) to isCopyInstrImpl (#133443)
2025-03-28 15:46:50 +00:00
RISCVInstrInfo.h
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
RISCVInstrInfo.td
[RISCV] Rename operands used for branch and compressed jump targets. NFC (#133364)
2025-03-28 12:32:32 -07:00
RISCVInstrInfoA.td
[RISCV] Remove unnecessary patterns from RISCVInstrInfoA.td. NFC
2024-12-17 10:24:50 -08:00
RISCVInstrInfoC.td
[RISCV] Rename operands used for branch and compressed jump targets. NFC (#133364)
2025-03-28 12:32:32 -07:00
RISCVInstrInfoD.td
[RISCV] Set mayRaiseFPException = 0 on FCVT_D_W(U). (#133200)
2025-03-27 07:45:42 -07:00
RISCVInstrInfoF.td
[RISCV] Use MnemonicAlias for 'fssr' and 'frsr'. NFC (#131877)
2025-03-18 14:04:45 -07:00
RISCVInstrInfoM.td
[RISCV][GISel] Move i32 patterns that aren't used by SelectionDAG to RISCVGISel.td. NFC (#102685)
2024-08-12 09:34:02 -07:00
RISCVInstrInfoSFB.td
[RISCV] Fix the operand types for shift instructions in RISCVInstrInfoSFB.td. NFC
2025-03-30 22:38:26 -07:00
RISCVInstrInfoV.td
[RISCV][NFC] Fix the comment for VALUVINoVm (#132730)
2025-03-24 17:49:53 +01:00
RISCVInstrInfoVPseudos.td
[RISCV] Use vsetvli instead of vlenb in Prologue/Epilogue (#113756)
2025-03-21 17:22:32 +08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Convert vsub.vx to vadd.vi if possible (#130669)
2025-03-10 16:20:14 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Convert vsub.vx to vadd.vi if possible (#130669)
2025-03-10 16:20:14 -07:00
RISCVInstrInfoXCV.td
[RISCV] Rename operands used for branch and compressed jump targets. NFC (#133364)
2025-03-28 12:32:32 -07:00
RISCVInstrInfoXMips.td
[RISCV] Simplify MIPS CCMov patterns. NFC (#125318)
2025-02-01 09:36:31 -08:00
RISCVInstrInfoXqccmp.td
[RISCV][Xqccmp] Correctly Parse/Disassemble pushfp (#133188)
2025-03-27 17:43:26 -07:00
RISCVInstrInfoXqci.td
[RISCV] Add Qualcomm uC Xqciio (External Input Output) extension (#132721)
2025-03-28 19:47:29 -07:00
RISCVInstrInfoXRivos.td
[RISCV] Initial codegen support for the XRivosVizip extension (#131933)
2025-03-29 15:25:56 -07:00
RISCVInstrInfoXSf.td
[RISCV] Remove ParserMatchClass and DecoderMethod from an operand only used by pseudos. NFC
2025-03-27 15:07:29 -07:00
RISCVInstrInfoXTHead.td
[RISCV] Merge DecoderNamespace for T-Head extensions. NFC (#130555)
2025-03-10 10:15:12 -07:00
RISCVInstrInfoXVentana.td
[RISCV] Remove IsRV64 from XVentanaCondOps patterns. (#100891)
2024-07-27 17:26:32 -07:00
RISCVInstrInfoXwch.td
[RISCV][NFCI] Rationalize Immediate Definitions (#120718)
2024-12-21 09:47:07 +00:00
RISCVInstrInfoZa.td
[RISCV] Rename some DecoderNamespaces and cleanup debug messages. NFC (#131409)
2025-03-17 12:49:08 -07:00
RISCVInstrInfoZalasr.td
[RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (#82914)
2024-12-17 00:19:45 -08:00
RISCVInstrInfoZb.td
[RISCV] Support Zb*/P Shared Instructions (#127160)
2025-02-15 22:26:02 +08:00
RISCVInstrInfoZc.td
[RISCV][Xqccmp] Correctly Parse/Disassemble pushfp (#133188)
2025-03-27 17:43:26 -07:00
RISCVInstrInfoZclsd.td
[RISCV] Add ($rs1) InstAliases with no immediate for Zilsd/Zclsd. (#132094)
2025-03-19 15:35:51 -07:00
RISCVInstrInfoZcmop.td
…
RISCVInstrInfoZfa.td
[RISCV][NFC] Adopt DiagnosticString interface (#126290)
2025-02-08 07:59:55 -08:00
RISCVInstrInfoZfbfmin.td
[RISCV] Remove RISCVISD::FP_ROUND_BF16.
2024-09-03 20:18:01 -07:00
RISCVInstrInfoZfh.td
[RISCV] Correct the predicates for the flh/fsh InstAlias and assembler pseudos to include Zfbfmin. (#131920)
2025-03-18 17:55:36 -07:00
RISCVInstrInfoZicbo.td
[RISCV] Remove unused MCOperandPredicate from simm12_lsb00000. NFC
2025-03-27 16:45:58 -07:00
RISCVInstrInfoZicfiss.td
…
RISCVInstrInfoZicond.td
…
RISCVInstrInfoZilsd.td
[RISCV] Add ($rs1) InstAliases with no immediate for Zilsd/Zclsd. (#132094)
2025-03-19 15:35:51 -07:00
RISCVInstrInfoZimop.td
…
RISCVInstrInfoZk.td
[RISCV] Combine RVBUnary and RVKUnary into classes that are more similar to ALU(W)_r(r/i). NFC (#111279)
2024-10-06 11:47:30 -07:00
RISCVInstrInfoZvfbf.td
[RISCV] Add VL and VTYPE to implicit uses on MC vector instructions that also use FRM (#129130)
2025-02-27 19:25:14 -08:00
RISCVInstrInfoZvk.td
[RISCV] Add vector hasAndNot to enable optimizations (#132438)
2025-03-26 10:40:00 +01:00
RISCVInstrInfoZvqdotq.td
[RISCV] Add assembler support for Zvqdotq. (#132118)
2025-03-20 08:38:15 -07:00
RISCVISelDAGToDAG.cpp
[RISCV] Remove duplicate check in SelectAddrRegImmLsb00000. NFC (#133372)
2025-03-28 12:39:59 +05:30
RISCVISelDAGToDAG.h
[RISCV] Convert vsub.vx to vadd.vi if possible (#130669)
2025-03-10 16:20:14 -07:00
RISCVISelLowering.cpp
[RISCV] Add combine for shadd family of instructions. (#130829)
2025-03-31 10:02:12 -04:00
RISCVISelLowering.h
[RISCV] Initial codegen support for the XRivosVizip extension (#131933)
2025-03-29 15:25:56 -07:00
RISCVLandingPadSetup.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00
RISCVLateBranchOpt.cpp
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
RISCVLoadStoreOptimizer.cpp
[RISCV] Generate MIPS load/store pair instructions (#124717)
2025-03-07 09:21:36 +01:00
RISCVMachineFunctionInfo.cpp
[RISCV] Update to Xqciint v0.4 (#130219)
2025-03-11 08:54:22 -07:00
RISCVMachineFunctionInfo.h
[RISCV] Update to Xqciint v0.4 (#130219)
2025-03-11 08:54:22 -07:00
RISCVMacroFusion.td
…
RISCVMakeCompressible.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVMergeBaseOffset.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVMoveMerger.cpp
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
RISCVOptWInstrs.cpp
[RISCV] Add PseudoCCMOVGPRNoX0 to RISCVOptWInstrs.
2025-01-31 15:09:11 -08:00
RISCVPfmCounters.td
[RISCV][llvm-exegesis] Add default Pfm cycle counter. (#121866)
2025-01-07 09:51:34 -08:00
RISCVPostRAExpandPseudoInsts.cpp
[RISCV] Correct the pass name for RISCVPostRAExpandPseudo.
2024-12-05 16:43:30 -08:00
RISCVProcessors.td
[RISCV] Tune flag for fast vrgather.vv (#124664)
2025-03-03 16:04:49 -08:00
RISCVProfiles.td
[RISCV] Use the 'B' extension in RISC-V profile definitions (#113942)
2024-11-10 07:18:05 +00:00
RISCVPushPopOptimizer.cpp
[RISCV] Simplify how we find combinable cm.pop+ret. (#130204)
2025-03-06 21:55:47 -08:00
RISCVRedundantCopyElimination.cpp
…
RISCVRegisterInfo.cpp
[RISCV] Refine location size for segment spill and fill (#133268)
2025-03-28 07:06:17 -07:00
RISCVRegisterInfo.h
[RISCV][RegAlloc] Add getCSRFirstUseCost for RISC-V (#131349)
2025-03-20 15:20:04 -04:00
RISCVRegisterInfo.td
[RISCV] Set AllocationPriority in line with LMUL (#131176)
2025-03-18 08:25:49 -07:00
RISCVSchedGenericOOO.td
[RISCV] Add a generic OOO CPU (#120712)
2025-02-14 17:35:02 +08:00
RISCVSchedMIPSP8700.td
[RISCV] Remove duplicate WriteRes<WriteJalr for MIPSP8700. (#123865)
2025-01-22 10:37:01 -08:00
RISCVSchedRocket.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSchedSiFive7.td
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVSchedSiFiveP400.td
[RISCV] Update some of the RVV memory ops in SiFive P400 & P600 sched models (#129575)
2025-03-17 15:29:36 -07:00
RISCVSchedSiFiveP500.td
[RISCV] Update the latency of floating point load in SiFive P500 scheduling model (#133165)
2025-03-27 11:00:07 -07:00
RISCVSchedSiFiveP600.td
[RISCV] Update some of the RVV memory ops in SiFive P400 & P600 sched models (#129575)
2025-03-17 15:29:36 -07:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Remove some unnecessary UnsupportedSched* that are implied by others. NFC
2025-01-21 18:00:52 -08:00
RISCVSchedSyntacoreSCR7.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSchedSyntacoreSCR345.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSchedTTAscalonD8.td
[RISC-V] Base scheduling model for tt-ascalon-d8 (#120160)
2024-12-20 15:30:17 -05:00
RISCVSchedule.td
[RISCV] Add missing ReadFMA16Addend in UnsupportedSchedZfh
2024-12-31 17:22:08 +08:00
RISCVScheduleV.td
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVScheduleXSf.td
…
RISCVScheduleZb.td
…
RISCVScheduleZvk.td
[RISCV] Assign separate PseudoVSHA2MS_VV opcodes for each SEW (#114317)
2024-10-31 10:21:14 -07:00
RISCVSchedXiangShanNanHu.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSelectionDAGInfo.cpp
[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)
2024-12-21 05:29:51 +03:00
RISCVSelectionDAGInfo.h
[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)
2024-12-21 05:29:51 +03:00
RISCVSubtarget.cpp
[RISCV] Generate MIPS load/store pair instructions (#124717)
2025-03-07 09:21:36 +01:00
RISCVSubtarget.h
[RISCV] Enable prefetching writes (#130561)
2025-03-11 11:39:21 +08:00
RISCVSystemOperands.td
[RISCV] Remove the mucounteren alternate name for CSR 0x320. (#132498)
2025-03-24 09:47:21 -07:00
RISCVTargetMachine.cpp
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
RISCVTargetMachine.h
[CodeGen] Move MISched target hooks into TargetMachine (#125700)
2025-02-05 11:41:37 +05:30
RISCVTargetObjectFile.cpp
[RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel
2025-03-29 11:08:13 -07:00
RISCVTargetObjectFile.h
[RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel
2025-03-29 11:08:13 -07:00
RISCVTargetTransformInfo.cpp
[RISCV][TTI] Adjust VLS shuffle costing to account for sub-mask reuse (#129793)
2025-03-29 15:18:44 -07:00
RISCVTargetTransformInfo.h
[RISCV] Don't vectorize for loops with small trip count (#132176)
2025-03-28 15:51:29 +08:00
RISCVVectorMaskDAGMutation.cpp
[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296)
2025-03-05 08:56:09 -08:00
RISCVVectorPeephole.cpp
[RISCV] Move the RISCVII namespaced enums into RISCVVType namespace in RISCVTargetParser.h. NFC (#127585)
2025-02-18 08:27:25 -08:00
RISCVVLOptimizer.cpp
[RISCV][VLOPT] Look through PHI instructions (#132236)
2025-03-24 09:26:09 -04:00
RISCVVMV0Elimination.cpp
[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination
2025-02-26 23:09:50 +08:00
RISCVZacasABIFix.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00