0731567a31
Due to delayed decision for ADD/SUB relocations, RISCV and LoongArch may go slow fragment walk path with available layout. When RISCV (or LoongArch in the future) don't need insert nops, that means relax is disabled. With available layout and not needing insert nops, the size of AlignFragment should be a constant. So we can add it to Displacement for folding A-B.
80 lines
2.3 KiB
ArmAsm
80 lines
2.3 KiB
ArmAsm
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+relax %s \
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# RUN: | llvm-readobj -r - | FileCheck -check-prefix RELAX %s
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# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=-relax %s \
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# RUN: | llvm-readobj -r - | FileCheck -check-prefix NORELAX %s
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+relax %s \
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# RUN: | llvm-readobj -r - | FileCheck -check-prefix RELAX %s
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=-relax %s \
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# RUN: | llvm-readobj -r - | FileCheck -check-prefix NORELAX %s
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# NORELAX: Relocations [
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# NORELAX-NEXT: .rela.text {
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# NORELAX-NEXT: R_RISCV_CALL_PLT
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# NORELAX-NEXT: }
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# NORELAX-NEXT: ]
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.globl G1
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.globl G2
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.globl G3
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.L1:
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G1:
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call extern
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.L2:
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G2:
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.p2align 3
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.L3:
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G3:
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.data
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.dword .L2-.L1
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.dword G2-G1
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.word .L2-.L1
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.word G2-G1
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.half .L2-.L1
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.half G2-G1
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.byte .L2-.L1
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.byte G2-G1
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.dword .L3-.L2
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.dword G3-G2
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.word .L3-.L2
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.word G3-G2
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.half .L3-.L2
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.half G3-G2
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.byte .L3-.L2
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.byte G3-G2
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# RELAX: .rela.data {
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# RELAX-NEXT: 0x0 R_RISCV_ADD64 .L2 0x0
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# RELAX-NEXT: 0x0 R_RISCV_SUB64 .L1 0x0
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# RELAX-NEXT: 0x8 R_RISCV_ADD64 G2 0x0
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# RELAX-NEXT: 0x8 R_RISCV_SUB64 G1 0x0
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# RELAX-NEXT: 0x10 R_RISCV_ADD32 .L2 0x0
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# RELAX-NEXT: 0x10 R_RISCV_SUB32 .L1 0x0
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# RELAX-NEXT: 0x14 R_RISCV_ADD32 G2 0x0
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# RELAX-NEXT: 0x14 R_RISCV_SUB32 G1 0x0
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# RELAX-NEXT: 0x18 R_RISCV_ADD16 .L2 0x0
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# RELAX-NEXT: 0x18 R_RISCV_SUB16 .L1 0x0
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# RELAX-NEXT: 0x1A R_RISCV_ADD16 G2 0x0
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# RELAX-NEXT: 0x1A R_RISCV_SUB16 G1 0x0
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# RELAX-NEXT: 0x1C R_RISCV_ADD8 .L2 0x0
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# RELAX-NEXT: 0x1C R_RISCV_SUB8 .L1 0x0
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# RELAX-NEXT: 0x1D R_RISCV_ADD8 G2 0x0
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# RELAX-NEXT: 0x1D R_RISCV_SUB8 G1 0x0
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# RELAX-NEXT: 0x1E R_RISCV_ADD64 .L3 0x0
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# RELAX-NEXT: 0x1E R_RISCV_SUB64 .L2 0x0
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# RELAX-NEXT: 0x26 R_RISCV_ADD64 G3 0x0
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# RELAX-NEXT: 0x26 R_RISCV_SUB64 G2 0x0
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# RELAX-NEXT: 0x2E R_RISCV_ADD32 .L3 0x0
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# RELAX-NEXT: 0x2E R_RISCV_SUB32 .L2 0x0
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# RELAX-NEXT: 0x32 R_RISCV_ADD32 G3 0x0
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# RELAX-NEXT: 0x32 R_RISCV_SUB32 G2 0x0
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# RELAX-NEXT: 0x36 R_RISCV_ADD16 .L3 0x0
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# RELAX-NEXT: 0x36 R_RISCV_SUB16 .L2 0x0
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# RELAX-NEXT: 0x38 R_RISCV_ADD16 G3 0x0
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# RELAX-NEXT: 0x38 R_RISCV_SUB16 G2 0x0
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# RELAX-NEXT: 0x3A R_RISCV_ADD8 .L3 0x0
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# RELAX-NEXT: 0x3A R_RISCV_SUB8 .L2 0x0
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# RELAX-NEXT: 0x3B R_RISCV_ADD8 G3 0x0
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# RELAX-NEXT: 0x3B R_RISCV_SUB8 G2 0x0
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# RELAX-NEXT: }
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