Michael Maitland 818e0272f5 [RISCV] Model integer min max instructions from Zbb execute in late-B ALU ...

We don't model the early vs late ALU so we just need to remove usage of
SiFivePipeA for these instructions.

2024-03-14 06:02:53 -07:00

..

div-fdiv.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

gpr-bypass-c.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

gpr-bypass.s

[RISCV] Model integer min max instructions from Zbb execute in late-B ALU

2024-03-14 06:02:53 -07:00

reductions.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

strided-load-store.s

[RISCV][llvm-mca] Use correct LMUL and SEW for strided loads and stores (#76869)

2024-01-04 15:40:30 -05:00

strided-load-x0.s

[RISCV][llvm-mca] Fix failing strided-load-x0.s test

2024-01-04 12:59:31 -08:00

vector-integer-arithmetic.s

[RISCV] Add SMLoc to expanded vector pseudoinstructions in AsmParser. (#84875)

2024-03-13 10:51:48 -07:00