Michael Maitland 818e0272f5 [RISCV] Model integer min max instructions from Zbb execute in late-B ALU ...

We don't model the early vs late ALU so we just need to remove usage of
SiFivePipeA for these instructions.

2024-03-14 06:02:53 -07:00

..

SiFive7

[RISCV] Model integer min max instructions from Zbb execute in late-B ALU

2024-03-14 06:02:53 -07:00

XiangShan

[RISCV] Add sched model for XiangShan-NanHu (#70232)

2024-02-12 15:00:54 +08:00

different-lmul-instruments.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

different-sew-instruments.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

disable-im.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

fractional-lmul-data.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

lit.local.cfg

…

lmul-instrument-at-start.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

lmul-instrument-in-middle.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

lmul-instrument-in-region.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

lmul-instrument-straddles-region.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

multiple-same-lmul-instruments.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

multiple-same-sew-instruments.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

needs-sew-but-only-lmul.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

no-vsetvli-to-start.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

riscv-lmul-instrument-no-data-is-err.s

[llvm-mca][RISCV] Add RISCV-SEW instrument

2023-07-14 12:12:04 -07:00

riscv-sew-instrument-no-data-is-err.s

[llvm-mca][RISCV] Add RISCV-SEW instrument

2023-07-14 12:12:04 -07:00

sew-instrument-at-start.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

sew-instrument-in-middle.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

sew-instrument-in-region.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

sew-instrument-straddles-region.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

unknown-instrument-is-err.s

…

unknown-lmul-is-err.s

[llvm-mca][RISCV] Add RISCV-SEW instrument

2023-07-14 12:12:04 -07:00

unknown-sew-is-err.s

[llvm-mca][RISCV] Add RISCV-SEW instrument

2023-07-14 12:12:04 -07:00

vle-vse.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

vsetivli-lmul-instrument.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

vsetivli-lmul-sew-instrument.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

vsetvli-lmul-instrument.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

vsetvli-lmul-sew-instrument.s

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00