d9570babf1
The Arithmetic, Load, and Store sequencers can accept instructions in parallel. The PipeV blocked that from happening since it became busy if any of the sequencers were busy. This change allows the sequencers to accept instructions in parallel. The VCQ accepts instructions from the the A Pipe and holds them until the vector unit is ready to dequeue them. The unit dequeues up to one instruction per cycle, in order, as soon as the sequencer for that type of instruction is avaliable. This resource is meant to be used for 1 cycle by all vector instructions, to model that only one vector instruction may be dequed at a time. The actual dequeueing into the sequencer is modeled by the VA, VL, and VS sequencer resources below. Each of them will only accept a single instruction at a time and remain busy for the number of cycles associated with that instruction.
98 lines
4.8 KiB
ArmAsm
98 lines
4.8 KiB
ArmAsm
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
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vsetvli zero, a0, e8, m1, tu, mu
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# LLVM-MCA-RISCV-LMUL M1
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vadd.vv v12, v12, v12
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vsetvli zero, a0, e8, m1, tu, mu
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# LLVM-MCA-RISCV-LMUL M1
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vadd.vv v12, v12, v12
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vsub.vv v12, v12, v12
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vsetvli zero, a0, e8, m4, tu, mu
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# LLVM-MCA-RISCV-LMUL M4
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vadd.vv v12, v12, v12
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vsub.vv v12, v12, v12
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# CHECK: Iterations: 1
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# CHECK-NEXT: Instructions: 8
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# CHECK-NEXT: Total Cycles: 29
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# CHECK-NEXT: Total uOps: 8
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# CHECK: Dispatch Width: 2
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# CHECK-NEXT: uOps Per Cycle: 0.28
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# CHECK-NEXT: IPC: 0.28
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# CHECK-NEXT: Block RThroughput: 27.0
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12
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# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12
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# CHECK-NEXT: 1 4 3.00 vsub.vv v12, v12, v12
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# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m4, tu, mu
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# CHECK-NEXT: 1 4 9.00 vadd.vv v12, v12, v12
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# CHECK-NEXT: 1 4 9.00 vsub.vv v12, v12, v12
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SiFive7FDiv
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# CHECK-NEXT: [1] - SiFive7IDiv
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# CHECK-NEXT: [2] - SiFive7PipeA
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# CHECK-NEXT: [3] - SiFive7PipeB
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# CHECK-NEXT: [4] - SiFive7VA
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# CHECK-NEXT: [5] - SiFive7VCQ
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# CHECK-NEXT: [6] - SiFive7VL
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# CHECK-NEXT: [7] - SiFive7VS
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
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# CHECK-NEXT: - - 3.00 - 27.00 5.00 - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
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# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v12
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# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v12
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# CHECK-NEXT: - - - - 3.00 1.00 - - vsub.vv v12, v12, v12
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# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m4, tu, mu
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# CHECK-NEXT: - - - - 9.00 1.00 - - vadd.vv v12, v12, v12
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# CHECK-NEXT: - - - - 9.00 1.00 - - vsub.vv v12, v12, v12
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# CHECK: Timeline view:
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# CHECK-NEXT: 0123456789
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# CHECK-NEXT: Index 0123456789 012345678
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# CHECK: [0,0] DeeE . . . . . . vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: [0,1] . DeeeE . . . . . vadd.vv v12, v12, v12
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# CHECK-NEXT: [0,2] . DeeE . . . . . vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: [0,3] . . DeeeE . . . . vadd.vv v12, v12, v12
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# CHECK-NEXT: [0,4] . . .DeeeE . . . vsub.vv v12, v12, v12
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# CHECK-NEXT: [0,5] . . . DeeE . . . vsetvli zero, a0, e8, m4, tu, mu
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# CHECK-NEXT: [0,6] . . . DeeeE. . . vadd.vv v12, v12, v12
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# CHECK-NEXT: [0,7] . . . . . DeeeE vsub.vv v12, v12, v12
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# CHECK: Average Wait times (based on the timeline view):
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# CHECK-NEXT: [0]: Executions
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# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
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# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
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# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
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# CHECK: [0] [1] [2] [3]
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# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
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# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
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# CHECK-NEXT: 4. 1 0.0 0.0 0.0 vsub.vv v12, v12, v12
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# CHECK-NEXT: 5. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m4, tu, mu
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# CHECK-NEXT: 6. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
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# CHECK-NEXT: 7. 1 0.0 0.0 0.0 vsub.vv v12, v12, v12
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# CHECK-NEXT: 1 0.0 0.0 0.0 <total>
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