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llvm-project/llvm/test/CodeGen/AVR
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Ayke aeeb9b5077
[AVR] Fix codegen after getConstant assertions got enabled (#152269) 
This fixes https://github.com/llvm/llvm-project/issues/152097

This commit fixes two instances of a (somewhat) recently enabled
assertion. One with a test, the other I can't reproduce (might be dead
code) but certainly looks like an instance of the same problem.

The PR that introduced the regression:
https://github.com/llvm/llvm-project/pull/117558

With this patch, the AVR backend is usable again for TinyGo.
2025-08-07 11:40:33 +02:00
..
atomics
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
calling-conv/c
[RegAlloc] Sort CopyHint by IsCSR (#131046)
2025-04-14 09:58:46 -04:00
features
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
inline-asm
[clang][AVR] Improve compatibility of inline assembly with avr-gcc (#136534)
2025-04-23 18:42:07 +08:00
integration
[AVR,test] Change llc -march= to -mtriple=
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intrinsics
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
pseudo
[AVR] Simplify SPWRITE on XMEGA (#147210)
2025-07-14 09:40:37 +08:00
add.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
addrspacecast.ll
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alloca.ll
[AVR,test] Change llc -march= to -mtriple=
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and.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
avr-rust-issue-123.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
base-with-add-like-constant-offset.ll
[SDAG] Apply or-disjoint in SelectionDAG::isBaseWithConstantOffset (#88493)
2024-04-15 13:59:48 +09:00
block-address-is-in-progmem-space.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
branch-relaxation-long-backward.ll
[AVR] Force to emit relocation slots for relative branch instructions (#145291)
2025-07-20 22:10:31 +08:00
branch-relaxation-long-forward.ll
[AVR] Force to emit relocation slots for relative branch instructions (#145291)
2025-07-20 22:10:31 +08:00
branch-relaxation.ll
[AVR,test] Change llc -march= to -mtriple=
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brind.ll
[AVR,test] Change llc -march= to -mtriple=
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bug-56423.ll
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bug-81911.ll
[PHIElimination] Revert #131837 #146320 #146337 (#146850)
2025-07-03 07:48:08 -04:00
bug-143247.ll
[AVR] Don't apply post-indexing on mismatched pointers (#145224)
2025-06-22 18:18:00 +08:00
call.ll
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clear-bss.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
cmp.ll
[AVR] Fix codegen after getConstant assertions got enabled (#152269)
2025-08-07 11:40:33 +02:00
com.ll
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copy-data-to-ram.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
ctlz.ll
[AVR,test] Change llc -march= to -mtriple=
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ctors.ll
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ctpop.ll
[AVR,test] Change llc -march= to -mtriple=
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cttz.ll
[AVR,test] Change llc -march= to -mtriple=
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directmem.ll
[AVR,test] Change llc -march= to -mtriple=
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div.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
dynalloca.ll
[RegAlloc] Sort CopyHint by IsCSR (#131046)
2025-04-14 09:58:46 -04:00
elpm.ll
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eor.ll
[AVR,test] Change llc -march= to -mtriple=
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expand-integer-failure.ll
[AVR,test] Change llc -march= to -mtriple=
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frame.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
frmidx-iterator-bug.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
global-aliases.ll
Introduce MCAsmInfo::UsesSetToEquateSymbol and prefer = to .set
2025-06-11 22:19:31 -07:00
hardware-mul.ll
[AVR] Fix a bug in selection of ANY_EXTEND (#132398)
2025-03-26 15:15:40 +01:00
high-pressure-on-ptrregs.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
icall-func-pointer-correct-addr-space.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
impossible-reg-to-reg-copy.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
interrupts.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
io.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
issue-58856-eicall.ll
…
issue-132203.ll
[AVR] Fix a bug in selection of ANY_EXTEND (#132398)
2025-03-26 15:15:40 +01:00
issue-cannot-select-bswap.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
issue-regalloc-stackframe-folding-earlyclobber.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
jmp-long.ll
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jmp.ll
[AVR] Force to emit relocation slots for relative branch instructions (#145291)
2025-07-20 22:10:31 +08:00
large-return-size.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
ldd-immediate-overflow.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
lit.local.cfg
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llrint.ll
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llround-conv.ll
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llvm.sincos.ll
RuntimeLibcalls: Really move default libcall handling to tablegen (#148780)
2025-08-04 08:32:00 +09:00
load.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
lower-formal-args-struct-return.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
lower-formal-arguments-assertion.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
lpmx.ll
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lrint.ll
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lround-conv.ll
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naked-fn-with-frame-pointer.ll
[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)
2024-10-18 09:35:42 +04:00
neg.ll
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no-clear-bss.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
no-copy-data.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
no-print-operand-twice.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
or.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
pr43443-ctor-alias.ll
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PR31344.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
PR31345.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
PR37143.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
pre-schedule.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
progmem-extended.ll
[AVR,test] Change llc -march= to -mtriple=
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progmem.ll
[AVR,test] Change llc -march= to -mtriple=
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rem.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
return.ll
[RegAlloc] Sort CopyHint by IsCSR (#131046)
2025-04-14 09:58:46 -04:00
rot.ll
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rotate.ll
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runtime-trig.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
rust-avr-bug-37.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
rust-avr-bug-95.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
rust-avr-bug-99.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
rust-avr-bug-112.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
rust-bug-98167.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
rust-trait-object.ll
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sections.ll
[CodeGen] Clean up tests that depend on implicit .text in MCAsmStreamer
2024-12-22 21:11:32 -08:00
select-must-add-unconditional-jump.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
sext.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
shift32.ll
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shift-expand.ll
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shift.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
sign-extension.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
sincos-soften-error.ll
DAG: Fall back to separate sin and cos when softening sincos (#147468)
2025-07-09 01:52:46 +09:00
smul-with-overflow.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
software-mul.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
std-immediate-overflow.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
std-ldd-immediate-overflow.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
stdwstk.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
store-undef.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
store.ll
[AVR,test] Change llc -march= to -mtriple=
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struct.ll
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sub.ll
[AVR,test] Change llc -march= to -mtriple=
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trunc.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
umul-with-overflow.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
umul.with.overflow.i16-bug.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
unaligned-atomic-ops.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
varargs.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
volatile-null.ll
[LangRef] Comment on validity of volatile ops on null (#139803)
2025-05-22 15:12:34 +02:00
xor.ll
[AVR,test] Change llc -march= to -mtriple=
2024-12-15 10:26:33 -08:00
zeroreg.ll
[AVR,test] Change llc -march= to -mtriple=
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zext.ll
[AVR,test] Change llc -march= to -mtriple=
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