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llvm-project/llvm/test/CodeGen/Hexagon/isel
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Sumanth Gundapaneni aaf2d078b6
[Hexagon] Clean up redundant transfer instructions. (#82663)
This patch adds a Hexagon specific backend pass that cleans up redundant
transfers after register allocation.
2024-02-22 17:31:37 -06:00
..
cmp-i1.ll
[Hexagon] Handle all compares of i1 and vNi1
2023-06-17 16:31:21 -07:00
cmp-v2i1.ll
[Hexagon] Handle all compares of i1 and vNi1
2023-06-17 16:31:21 -07:00
cmp-v4i1.ll
[Hexagon] Handle all compares of i1 and vNi1
2023-06-17 16:31:21 -07:00
cmp-v8i1.ll
[Hexagon] Handle all compares of i1 and vNi1
2023-06-17 16:31:21 -07:00
extload-i1.ll
…
logical.ll
[DAGCombiner] Reassociate the operands from (OR (OR(CMP1, CMP2)), CMP3) to (OR (OR(CMP1, CMP3)), CMP2)
2023-08-08 20:08:01 -07:00
mulh-scalar.ll
…
select-i1.ll
[Hexagon] Add missing patterns for boolean [v]selects
2023-06-17 17:15:07 -07:00
select-vec.ll
[Hexagon] Clean up redundant transfer instructions. (#82663)
2024-02-22 17:31:37 -06:00
trunc-vNi1.ll
…
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