119216ead1
This changes the intrinsic definitions for shifts to use IntArg, which in turn changes how the shifts are represented in SDAG to use TargetConstant (and fixes up a number of ISel lowering places too). The vecshift immediates are changed from ImmLeaf to TImmLeaf to keep them matching the TargetConstant. On the GISel side the constant shift amounts are then represented as immediate operands, not separate constants. The end result is that this allows a few more patterns to match in GISel.
149 lines
4.7 KiB
LLVM
149 lines
4.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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define i64 @select_ogt_float(float %a, float %b) {
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; CHECK-SD-LABEL: select_ogt_float:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: fcmp s0, s1
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; CHECK-SD-NEXT: mov w8, #4 // =0x4
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; CHECK-SD-NEXT: csel x0, x8, xzr, gt
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: select_ogt_float:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: fcmp s0, s1
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; CHECK-GI-NEXT: cset w8, gt
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; CHECK-GI-NEXT: lsl x0, x8, #2
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; CHECK-GI-NEXT: ret
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entry:
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%cc = fcmp ogt float %a, %b
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%sel = select i1 %cc, i64 4, i64 0
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ret i64 %sel
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}
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define i64 @select_ule_float_inverse(float %a, float %b) {
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; CHECK-SD-LABEL: select_ule_float_inverse:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: fcmp s0, s1
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; CHECK-SD-NEXT: mov w8, #4 // =0x4
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; CHECK-SD-NEXT: csel x0, xzr, x8, le
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: select_ule_float_inverse:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: fcmp s0, s1
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; CHECK-GI-NEXT: cset w8, gt
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; CHECK-GI-NEXT: lsl x0, x8, #2
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; CHECK-GI-NEXT: ret
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entry:
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%cc = fcmp ule float %a, %b
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%sel = select i1 %cc, i64 0, i64 4
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ret i64 %sel
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}
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define i64 @select_eq_i32(i32 %a, i32 %b) {
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; CHECK-SD-LABEL: select_eq_i32:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: mov w8, #4 // =0x4
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; CHECK-SD-NEXT: cmp w0, w1
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; CHECK-SD-NEXT: csel x0, x8, xzr, eq
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: select_eq_i32:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: cmp w0, w1
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; CHECK-GI-NEXT: cset w8, eq
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; CHECK-GI-NEXT: lsl x0, x8, #2
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; CHECK-GI-NEXT: ret
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entry:
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%cc = icmp eq i32 %a, %b
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%sel = select i1 %cc, i64 4, i64 0
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ret i64 %sel
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}
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define i64 @select_ne_i32_inverse(i32 %a, i32 %b) {
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; CHECK-SD-LABEL: select_ne_i32_inverse:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: mov w8, #4 // =0x4
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; CHECK-SD-NEXT: cmp w0, w1
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; CHECK-SD-NEXT: csel x0, xzr, x8, ne
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: select_ne_i32_inverse:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: cmp w0, w1
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; CHECK-GI-NEXT: cset w8, eq
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; CHECK-GI-NEXT: lsl x0, x8, #2
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; CHECK-GI-NEXT: ret
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entry:
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%cc = icmp ne i32 %a, %b
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%sel = select i1 %cc, i64 0, i64 4
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ret i64 %sel
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}
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define <2 x double> @select_olt_load_cmp(<2 x double> %a, ptr %src) {
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; CHECK-SD-LABEL: select_olt_load_cmp:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: ldr d1, [x0]
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; CHECK-SD-NEXT: fcmgt v1.2s, v1.2s, #0.0
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; CHECK-SD-NEXT: sshll v1.2d, v1.2s, #0
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; CHECK-SD-NEXT: and v0.16b, v1.16b, v0.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: select_olt_load_cmp:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: ldr d1, [x0]
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; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
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; CHECK-GI-NEXT: fcmgt v1.2s, v1.2s, #0.0
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; CHECK-GI-NEXT: ushll v1.2d, v1.2s, #0
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; CHECK-GI-NEXT: shl v1.2d, v1.2d, #63
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; CHECK-GI-NEXT: cmlt v1.2d, v1.2d, #0
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; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b
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; CHECK-GI-NEXT: ret
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entry:
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%l = load <2 x float>, ptr %src, align 4
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%cmp = fcmp olt <2 x float> zeroinitializer, %l
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%sel = select <2 x i1> %cmp, <2 x double> %a, <2 x double> zeroinitializer
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ret <2 x double> %sel
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}
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define <4 x i32> @select_icmp_sgt(<4 x i32> %a, <4 x i8> %b) {
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; CHECK-SD-LABEL: select_icmp_sgt:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: shl v1.4h, v1.4h, #8
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; CHECK-SD-NEXT: sshr v1.4h, v1.4h, #8
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; CHECK-SD-NEXT: cmgt v1.4h, v1.4h, #0
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; CHECK-SD-NEXT: sshll v1.4s, v1.4h, #0
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; CHECK-SD-NEXT: bic v0.16b, v0.16b, v1.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: select_icmp_sgt:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: mov w8, #0 // =0x0
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; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b
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; CHECK-GI-NEXT: fmov s2, w8
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; CHECK-GI-NEXT: mov v2.b[1], w8
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; CHECK-GI-NEXT: mov v2.b[2], w8
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; CHECK-GI-NEXT: mov v2.b[3], w8
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; CHECK-GI-NEXT: cmgt v1.8b, v1.8b, v2.8b
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; CHECK-GI-NEXT: umov w8, v1.b[0]
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; CHECK-GI-NEXT: umov w9, v1.b[1]
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; CHECK-GI-NEXT: fmov s2, w8
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; CHECK-GI-NEXT: umov w8, v1.b[2]
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; CHECK-GI-NEXT: mov v2.s[1], w9
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; CHECK-GI-NEXT: umov w9, v1.b[3]
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; CHECK-GI-NEXT: mov v2.s[2], w8
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; CHECK-GI-NEXT: mov v2.s[3], w9
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; CHECK-GI-NEXT: shl v1.4s, v2.4s, #31
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; CHECK-GI-NEXT: cmlt v1.4s, v1.4s, #0
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; CHECK-GI-NEXT: bic v0.16b, v0.16b, v1.16b
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; CHECK-GI-NEXT: ret
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entry:
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%cmp = icmp sgt <4 x i8> %b, zeroinitializer
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%sel = select <4 x i1> %cmp, <4 x i32> zeroinitializer, <4 x i32> %a
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ret <4 x i32> %sel
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; CHECK: {{.*}}
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