36cb33bbca
The patch add branch hint for AtomicExpandImpl::expandAtomicCmpXchg, For
example: in PowerPC, it support branch hint as
```
loop:
lwarx r6,0,r3 # load and reserve
cmpw r4,r6 #1st 2 operands equal? bne- exit #skip if not
bne- exit #skip if not
stwcx. r5,0,r3 #store new value if still res’ved bne- loop #loop if lost reservation
bne- loop #loop if lost reservation
exit:
mr r4,r6 #return value from storage
```
`-` hints not taken,
`+` hints taken,
103 lines
3.8 KiB
LLVM
103 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; Test the generation of asm for the function:
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; int foo(_Atomic int *cp, int *old, int c) {
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; return atomic_compare_exchange_weak_explicit(cp, old, c, __ATOMIC_RELAXED, __ATOMIC_RELAXED);
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; }
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; RUN: llc < %s -ppc-asm-full-reg-names -mtriple=powerpc-ibm-aix -mcpu=pwr8 -verify-machineinstrs \
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; RUN: | FileCheck %s --check-prefix=CHECK
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; RUN: llc < %s -ppc-asm-full-reg-names -mtriple=powerpc64-ibm-aix -mcpu=pwr8 -verify-machineinstrs \
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; RUN: | FileCheck %s --check-prefix=CHECK64
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define i32 @foo(ptr noundef %cp, ptr noundef %old, i32 noundef %c) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stw r3, -4(r1)
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; CHECK-NEXT: stw r4, -8(r1)
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; CHECK-NEXT: lwz r7, 0(r4)
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; CHECK-NEXT: stw r5, -12(r1)
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; CHECK-NEXT: stw r5, -16(r1)
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; CHECK-NEXT: lwarx r6, 0, r3
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; CHECK-NEXT: cmplw r6, r7
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; CHECK-NEXT: bne- cr0, L..BB0_5
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; CHECK-NEXT: # %bb.1: # %cmpxchg.fencedstore
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; CHECK-NEXT: creqv 4*cr5+lt, 4*cr5+lt, 4*cr5+lt
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; CHECK-NEXT: stwcx. r5, 0, r3
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; CHECK-NEXT: bne- cr0, L..BB0_5
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; CHECK-NEXT: # %bb.2: # %cmpxchg.end
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; CHECK-NEXT: bc 12, 4*cr5+lt, L..BB0_4
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; CHECK-NEXT: L..BB0_3: # %cmpxchg.store_expected
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; CHECK-NEXT: stw r6, 0(r4)
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; CHECK-NEXT: L..BB0_4: # %cmpxchg.continue
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; CHECK-NEXT: li r3, 0
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; CHECK-NEXT: li r4, 1
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; CHECK-NEXT: isel r3, r4, r3, 4*cr5+lt
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; CHECK-NEXT: stb r3, -17(r1)
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; CHECK-NEXT: blr
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; CHECK-NEXT: L..BB0_5: # %cmpxchg.failure
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; CHECK-NEXT: crxor 4*cr5+lt, 4*cr5+lt, 4*cr5+lt
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; CHECK-NEXT: b L..BB0_3
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;
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; CHECK64-LABEL: foo:
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; CHECK64: # %bb.0: # %entry
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; CHECK64-NEXT: std r3, -8(r1)
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; CHECK64-NEXT: std r4, -16(r1)
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; CHECK64-NEXT: lwz r7, 0(r4)
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; CHECK64-NEXT: stw r5, -20(r1)
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; CHECK64-NEXT: stw r5, -24(r1)
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; CHECK64-NEXT: lwarx r6, 0, r3
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; CHECK64-NEXT: cmplw r6, r7
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; CHECK64-NEXT: bne- cr0, L..BB0_5
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; CHECK64-NEXT: # %bb.1: # %cmpxchg.fencedstore
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; CHECK64-NEXT: creqv 4*cr5+lt, 4*cr5+lt, 4*cr5+lt
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; CHECK64-NEXT: stwcx. r5, 0, r3
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; CHECK64-NEXT: bne- cr0, L..BB0_5
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; CHECK64-NEXT: # %bb.2: # %cmpxchg.end
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; CHECK64-NEXT: bc 12, 4*cr5+lt, L..BB0_4
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; CHECK64-NEXT: L..BB0_3: # %cmpxchg.store_expected
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; CHECK64-NEXT: stw r6, 0(r4)
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; CHECK64-NEXT: L..BB0_4: # %cmpxchg.continue
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; CHECK64-NEXT: li r3, 0
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; CHECK64-NEXT: li r4, 1
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; CHECK64-NEXT: isel r3, r4, r3, 4*cr5+lt
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; CHECK64-NEXT: li r4, 1
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; CHECK64-NEXT: stb r3, -25(r1)
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; CHECK64-NEXT: li r3, 0
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; CHECK64-NEXT: isel r3, r4, r3, 4*cr5+lt
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; CHECK64-NEXT: blr
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; CHECK64-NEXT: L..BB0_5: # %cmpxchg.failure
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; CHECK64-NEXT: crxor 4*cr5+lt, 4*cr5+lt, 4*cr5+lt
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; CHECK64-NEXT: b L..BB0_3
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entry:
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%cp.addr = alloca ptr, align 4
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%old.addr = alloca ptr, align 4
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%c.addr = alloca i32, align 4
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%.atomictmp = alloca i32, align 4
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%cmpxchg.bool = alloca i8, align 1
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store ptr %cp, ptr %cp.addr, align 4
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store ptr %old, ptr %old.addr, align 4
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store i32 %c, ptr %c.addr, align 4
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%0 = load ptr, ptr %cp.addr, align 4
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%1 = load ptr, ptr %old.addr, align 4
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%2 = load i32, ptr %c.addr, align 4
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store i32 %2, ptr %.atomictmp, align 4
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%3 = load i32, ptr %1, align 4
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%4 = load i32, ptr %.atomictmp, align 4
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%5 = cmpxchg weak ptr %0, i32 %3, i32 %4 monotonic monotonic, align 4
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%6 = extractvalue { i32, i1 } %5, 0
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%7 = extractvalue { i32, i1 } %5, 1
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br i1 %7, label %cmpxchg.continue, label %cmpxchg.store_expected
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cmpxchg.store_expected: ; preds = %entry
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store i32 %6, ptr %1, align 4
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br label %cmpxchg.continue
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cmpxchg.continue: ; preds = %cmpxchg.store_expected, %entry
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%storedv = zext i1 %7 to i8
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store i8 %storedv, ptr %cmpxchg.bool, align 1
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%8 = load i8, ptr %cmpxchg.bool, align 1
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%loadedv = trunc i8 %8 to i1
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%conv = zext i1 %loadedv to i32
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ret i32 %conv
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}
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