1eb575dcae
The result type of the vector extend intrinsics generated by the BUILD_VECTOR lowering code should match how they are actually defined. Currently the result type is defaulting to the operand type there. This can conflict with calls to the same intrinsic from other paths.
69 lines
2.2 KiB
LLVM
69 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-aix-xcoff \
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; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc-aix-xcoff \
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; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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define dso_local noundef <8 x i16> @v103s() local_unnamed_addr {
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; CHECK-LABEL: v103s:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxspltib v2, 103
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; CHECK-NEXT: vupklsb v2, v2
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; CHECK-NEXT: blr
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entry:
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ret <8 x i16> splat (i16 103)
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}
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define dso_local noundef <2 x i64> @v103l() local_unnamed_addr {
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; CHECK-LABEL: v103l:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxspltib v2, 103
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; CHECK-NEXT: vextsb2d v2, v2
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; CHECK-NEXT: blr
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entry:
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ret <2 x i64> splat (i64 103)
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}
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define dso_local noundef <4 x i32> @v103i() local_unnamed_addr {
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; CHECK-LABEL: v103i:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxspltib v2, 103
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; CHECK-NEXT: vextsb2w v2, v2
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; CHECK-NEXT: blr
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entry:
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ret <4 x i32> splat (i32 103)
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}
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define dso_local noundef <2 x i64> @v11l() local_unnamed_addr {
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; CHECK-LABEL: v11l:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vspltisw v2, -11
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; CHECK-NEXT: vupklsw v2, v2
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; CHECK-NEXT: blr
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entry:
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ret <2 x i64> splat (i64 -11)
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}
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declare <4 x i32> @llvm.ppc.altivec.vextsb2w(<16 x i8>)
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define i32 @crash(ptr %p) {
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; CHECK-LABEL: crash:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxspltib v2, 127
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; CHECK-NEXT: vextsb2w v2, v2
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; CHECK-NEXT: stxv v2, 0(r3)
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; CHECK-NEXT: li r3, 0
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; CHECK-NEXT: stxv v2, 0(0)
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; CHECK-NEXT: blr
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entry:
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store <4 x i32> <i32 127, i32 127, i32 127, i32 127>, ptr %p, align 16
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%0 = call <4 x i32> @llvm.ppc.altivec.vextsb2w(<16 x i8> <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127>)
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store <4 x i32> %0, ptr null, align 16
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ret i32 0
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}
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