e71f327b46
Which is under discussion in https://github.com/llvm/llvm-project/issues/179036 Add new options -ffixed_r{8-15} for clang X86 target, like option "-ffixed_x" for RISCV/AArch64 target. Also, add target-feature +reserve-r{8-15} for the X86 backend. The registers which are specified reserved will not be used in RegAlloc/CalleeSave. Then the reserved registers can be maintained by user. It will be useful for the runtime/interpreter implementation. Other registers are used in specific instructions or mechanism, so they can't be reserved.
The LLVM Compiler Infrastructure
Welcome to the LLVM project!
This repository contains the source code for LLVM, a toolkit for the construction of highly optimized compilers, optimizers, and run-time environments.
The LLVM project has multiple components. The core of the project is itself called "LLVM". This contains all of the tools, libraries, and header files needed to process intermediate representations and convert them into object files. Tools include an assembler, disassembler, bitcode analyzer, and bitcode optimizer.
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