zhouguangyuan0718 e71f327b46
[X86] support reserve r8~r15 on X86_64 (#180242)
Which is under discussion in
https://github.com/llvm/llvm-project/issues/179036

Add new options -ffixed_r{8-15} for clang X86 target, like option
"-ffixed_x" for RISCV/AArch64 target.
Also, add target-feature +reserve-r{8-15} for the X86 backend.

The registers which are specified reserved will not be used in
RegAlloc/CalleeSave. Then the reserved registers can be maintained by
user. It will be useful for the runtime/interpreter implementation.

Other registers are used in specific instructions or mechanism, so they
can't be reserved.
2026-03-03 22:42:49 +00:00
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