6da1966bc5
This adds `RISCVScheduleXSf.td` with `SchedWrite` definitions for all VCIX instructions and uses it in `RISCVSchedSiFive7.td` to set default latencies for these instructions, helping with issue https://github.com/llvm/llvm-project/issues/83391. Of course these default latencies cannot be accurate (since each coprocessor will have different latencies), but this seems to be enough to avoid some of the problematic behavior described in the bug. In any case, this seems to be enough to help with #83391 in our internal testing. A subsequent discussion is how to structure the code such that it's easier for downstream consumers of this to use `SiFive7` scheduling model with accurate VCIX latencies. But we can probably have a separate issue to discuss that.
300 lines
13 KiB
TableGen
300 lines
13 KiB
TableGen
//===-- RISCVSchedule.td - RISC-V Scheduling Definitions ---*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// Define scheduler resources associated with def operands.
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def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
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def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
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def WriteShiftImm : SchedWrite; // 32 or 64-bit shift by immediate operations
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def WriteShiftImm32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
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def WriteShiftReg : SchedWrite; // 32 or 64-bit shift by immediate operations
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def WriteShiftReg32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
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def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide
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def WriteIDiv32 : SchedWrite; // 32-bit divide on RV64I
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def WriteIRem : SchedWrite; // 32-bit or 64-bit remainder
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def WriteIRem32 : SchedWrite; // 32-bit remainder on RV64I
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def WriteIMul : SchedWrite; // 32-bit or 64-bit multiply
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def WriteIMul32 : SchedWrite; // 32-bit multiply on RV64I
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def WriteJmp : SchedWrite; // Jump
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def WriteJal : SchedWrite; // Jump and link
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def WriteJalr : SchedWrite; // Jump and link register
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def WriteNop : SchedWrite;
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def WriteLDB : SchedWrite; // Load byte
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def WriteLDH : SchedWrite; // Load half-word
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def WriteLDW : SchedWrite; // Load word
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def WriteLDD : SchedWrite; // Load double-word
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def WriteCSR : SchedWrite; // CSR instructions
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def WriteSTB : SchedWrite; // Store byte
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def WriteSTH : SchedWrite; // Store half-word
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def WriteSTW : SchedWrite; // Store word
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def WriteSTD : SchedWrite; // Store double-word
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def WriteAtomicB : SchedWrite; //Atomic memory operation byte size
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def WriteAtomicH : SchedWrite; //Atomic memory operation halfword size
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def WriteAtomicW : SchedWrite; //Atomic memory operation word size
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def WriteAtomicD : SchedWrite; //Atomic memory operation double word size
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def WriteAtomicLDW : SchedWrite; // Atomic load word
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def WriteAtomicLDD : SchedWrite; // Atomic load double word
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def WriteAtomicSTW : SchedWrite; // Atomic store word
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def WriteAtomicSTD : SchedWrite; // Atomic store double word
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def WriteFAdd16 : SchedWrite; // 16-bit floating point addition/subtraction
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def WriteFAdd32 : SchedWrite; // 32-bit floating point addition/subtraction
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def WriteFAdd64 : SchedWrite; // 64-bit floating point addition/subtraction
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def WriteFMul16 : SchedWrite; // 16-bit floating point multiply
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def WriteFMul32 : SchedWrite; // 32-bit floating point multiply
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def WriteFMul64 : SchedWrite; // 64-bit floating point multiply
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def WriteFMA16 : SchedWrite; // 16-bit floating point fused multiply-add
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def WriteFMA32 : SchedWrite; // 32-bit floating point fused multiply-add
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def WriteFMA64 : SchedWrite; // 64-bit floating point fused multiply-add
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def WriteFDiv16 : SchedWrite; // 16-bit floating point divide
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def WriteFDiv32 : SchedWrite; // 32-bit floating point divide
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def WriteFDiv64 : SchedWrite; // 64-bit floating point divide
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def WriteFSqrt16 : SchedWrite; // 16-bit floating point sqrt
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def WriteFSqrt32 : SchedWrite; // 32-bit floating point sqrt
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def WriteFSqrt64 : SchedWrite; // 64-bit floating point sqrt
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// Integer to float conversions
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def WriteFCvtI32ToF16 : SchedWrite;
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def WriteFCvtI32ToF32 : SchedWrite;
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def WriteFCvtI32ToF64 : SchedWrite;
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def WriteFCvtI64ToF16 : SchedWrite; // RV64I only
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def WriteFCvtI64ToF32 : SchedWrite; // RV64I only
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def WriteFCvtI64ToF64 : SchedWrite; // RV64I only
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//Float to integer conversions
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def WriteFCvtF16ToI32 : SchedWrite;
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def WriteFCvtF16ToI64 : SchedWrite; // RV64I only
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def WriteFCvtF32ToI32 : SchedWrite;
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def WriteFCvtF32ToI64 : SchedWrite; // RV64I only
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def WriteFCvtF64ToI32 : SchedWrite;
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def WriteFCvtF64ToI64 : SchedWrite; // RV64I only
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// Float to float conversions
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def WriteFCvtF32ToF64 : SchedWrite;
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def WriteFCvtF64ToF32 : SchedWrite;
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def WriteFCvtF16ToF32 : SchedWrite;
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def WriteFCvtF32ToF16 : SchedWrite;
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def WriteFCvtF16ToF64 : SchedWrite;
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def WriteFCvtF64ToF16 : SchedWrite;
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// Zfa found instructions.
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def WriteFRoundF32 : SchedWrite;
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def WriteFRoundF64 : SchedWrite;
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def WriteFRoundF16 : SchedWrite;
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def WriteFClass16 : SchedWrite; // 16-bit floating point classify
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def WriteFClass32 : SchedWrite; // 32-bit floating point classify
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def WriteFClass64 : SchedWrite; // 64-bit floating point classify
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def WriteFCmp16 : SchedWrite; // 16-bit floating point compare
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def WriteFCmp32 : SchedWrite; // 32-bit floating point compare
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def WriteFCmp64 : SchedWrite; // 64-bit floating point compare
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def WriteFSGNJ16 : SchedWrite; // 16-bit floating point sign-injection
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def WriteFSGNJ32 : SchedWrite; // 32-bit floating point sign-injection
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def WriteFSGNJ64 : SchedWrite; // 64-bit floating point sign-injection
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def WriteFMinMax16 : SchedWrite; // 16-bit floating point min or max
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def WriteFMinMax32 : SchedWrite; // 32-bit floating point min or max
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def WriteFMinMax64 : SchedWrite; // 64-bit floating point min or max
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def WriteFMovF16ToI16 : SchedWrite;
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def WriteFMovI16ToF16 : SchedWrite;
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def WriteFMovF32ToI32 : SchedWrite;
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def WriteFMovI32ToF32 : SchedWrite;
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def WriteFMovF64ToI64 : SchedWrite; // RV64I only
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def WriteFMovI64ToF64 : SchedWrite; // RV64I only
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def WriteFLI16 : SchedWrite; // Floating point constant load
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def WriteFLI32 : SchedWrite; // Floating point constant load
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def WriteFLI64 : SchedWrite; // Floating point constant load
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def WriteFLD16 : SchedWrite; // Floating point sp load
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def WriteFLD32 : SchedWrite; // Floating point sp load
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def WriteFLD64 : SchedWrite; // Floating point dp load
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def WriteFST16 : SchedWrite; // Floating point sp store
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def WriteFST32 : SchedWrite; // Floating point sp store
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def WriteFST64 : SchedWrite; // Floating point dp store
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// short forward branch for Bullet
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def WriteSFB : SchedWrite;
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def ReadSFBJmp : SchedRead;
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def ReadSFBALU : SchedRead;
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/// Define scheduler resources associated with use operands.
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def ReadJmp : SchedRead;
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def ReadJalr : SchedRead;
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def ReadCSR : SchedRead;
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def ReadMemBase : SchedRead;
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def ReadFMemBase : SchedRead;
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def ReadStoreData : SchedRead;
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def ReadFStoreData : SchedRead;
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def ReadIALU : SchedRead;
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def ReadIALU32 : SchedRead; // 32-bit integer ALU operations on RV64I
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def ReadShiftImm : SchedRead;
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def ReadShiftImm32 : SchedRead; // 32-bit shift by immediate operations on RV64Ix
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def ReadShiftReg : SchedRead;
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def ReadShiftReg32 : SchedRead; // 32-bit shift by register operations on RV64Ix
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def ReadIDiv : SchedRead;
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def ReadIDiv32 : SchedRead;
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def ReadIRem : SchedRead;
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def ReadIRem32 : SchedRead;
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def ReadIMul : SchedRead;
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def ReadIMul32 : SchedRead;
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def ReadAtomicBA : SchedRead;
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def ReadAtomicBD : SchedRead;
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def ReadAtomicHA : SchedRead;
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def ReadAtomicHD : SchedRead;
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def ReadAtomicWA : SchedRead;
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def ReadAtomicWD : SchedRead;
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def ReadAtomicDA : SchedRead;
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def ReadAtomicDD : SchedRead;
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def ReadAtomicLDW : SchedRead; // Atomic load word
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def ReadAtomicLDD : SchedRead; // Atomic load double word
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def ReadAtomicSTW : SchedRead; // Atomic store word
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def ReadAtomicSTD : SchedRead; // Atomic store double word
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def ReadFAdd16 : SchedRead; // 16-bit floating point addition/subtraction
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def ReadFAdd32 : SchedRead; // 32-bit floating point addition/subtraction
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def ReadFAdd64 : SchedRead; // 64-bit floating point addition/subtraction
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def ReadFMul16 : SchedRead; // 16-bit floating point multiply
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def ReadFMul32 : SchedRead; // 32-bit floating point multiply
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def ReadFMul64 : SchedRead; // 64-bit floating point multiply
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def ReadFMA16 : SchedRead; // 16-bit floating point fused multiply-add
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def ReadFMA16Addend : SchedRead; // 16-bit floating point fused multiply-add (addend)
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def ReadFMA32 : SchedRead; // 32-bit floating point fused multiply-add
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def ReadFMA32Addend : SchedRead; // 32-bit floating point fused multiply-add (addend)
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def ReadFMA64 : SchedRead; // 64-bit floating point fused multiply-add
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def ReadFMA64Addend : SchedRead; // 64-bit floating point fused multiply-add (addend)
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def ReadFDiv16 : SchedRead; // 16-bit floating point divide
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def ReadFDiv32 : SchedRead; // 32-bit floating point divide
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def ReadFDiv64 : SchedRead; // 64-bit floating point divide
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def ReadFSqrt16 : SchedRead; // 16-bit floating point sqrt
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def ReadFSqrt32 : SchedRead; // 32-bit floating point sqrt
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def ReadFSqrt64 : SchedRead; // 64-bit floating point sqrt
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def ReadFCmp16 : SchedRead;
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def ReadFCmp32 : SchedRead;
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def ReadFCmp64 : SchedRead;
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def ReadFSGNJ16 : SchedRead;
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def ReadFSGNJ32 : SchedRead;
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def ReadFSGNJ64 : SchedRead;
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def ReadFMinMax16 : SchedRead;
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def ReadFMinMax32 : SchedRead;
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def ReadFMinMax64 : SchedRead;
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def ReadFCvtF16ToI32 : SchedRead;
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def ReadFCvtF16ToI64 : SchedRead;
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def ReadFCvtF32ToI32 : SchedRead;
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def ReadFCvtF32ToI64 : SchedRead;
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def ReadFCvtF64ToI32 : SchedRead;
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def ReadFCvtF64ToI64 : SchedRead;
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def ReadFCvtI32ToF16 : SchedRead;
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def ReadFCvtI32ToF32 : SchedRead;
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def ReadFCvtI32ToF64 : SchedRead;
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def ReadFCvtI64ToF16 : SchedRead;
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def ReadFCvtI64ToF32 : SchedRead;
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def ReadFCvtI64ToF64 : SchedRead;
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def ReadFMovF16ToI16 : SchedRead;
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def ReadFMovI16ToF16 : SchedRead;
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def ReadFMovF32ToI32 : SchedRead;
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def ReadFMovI32ToF32 : SchedRead;
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def ReadFMovF64ToI64 : SchedRead;
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def ReadFMovI64ToF64 : SchedRead;
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def ReadFCvtF32ToF64 : SchedRead;
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def ReadFCvtF64ToF32 : SchedRead;
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def ReadFCvtF16ToF32 : SchedRead;
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def ReadFCvtF32ToF16 : SchedRead;
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def ReadFCvtF16ToF64 : SchedRead;
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def ReadFCvtF64ToF16 : SchedRead;
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def ReadFRoundF16 : SchedRead;
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def ReadFRoundF32 : SchedRead;
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def ReadFRoundF64 : SchedRead;
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def ReadFClass16 : SchedRead;
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def ReadFClass32 : SchedRead;
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def ReadFClass64 : SchedRead;
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multiclass UnsupportedSchedZfh {
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let Unsupported = true in {
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def : WriteRes<WriteFAdd16, []>;
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def : WriteRes<WriteFClass16, []>;
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def : WriteRes<WriteFCvtF16ToF64, []>;
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def : WriteRes<WriteFCvtF64ToF16, []>;
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def : WriteRes<WriteFCvtI64ToF16, []>;
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def : WriteRes<WriteFCvtF32ToF16, []>;
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def : WriteRes<WriteFCvtI32ToF16, []>;
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def : WriteRes<WriteFCvtF16ToI64, []>;
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def : WriteRes<WriteFCvtF16ToF32, []>;
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def : WriteRes<WriteFCvtF16ToI32, []>;
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def : WriteRes<WriteFDiv16, []>;
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def : WriteRes<WriteFCmp16, []>;
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def : WriteRes<WriteFLD16, []>;
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def : WriteRes<WriteFMA16, []>;
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def : WriteRes<WriteFMinMax16, []>;
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def : WriteRes<WriteFMul16, []>;
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def : WriteRes<WriteFMovI16ToF16, []>;
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def : WriteRes<WriteFMovF16ToI16, []>;
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def : WriteRes<WriteFSGNJ16, []>;
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def : WriteRes<WriteFST16, []>;
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def : WriteRes<WriteFSqrt16, []>;
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def : ReadAdvance<ReadFAdd16, 0>;
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def : ReadAdvance<ReadFClass16, 0>;
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def : ReadAdvance<ReadFCvtF16ToF64, 0>;
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def : ReadAdvance<ReadFCvtF64ToF16, 0>;
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def : ReadAdvance<ReadFCvtI64ToF16, 0>;
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def : ReadAdvance<ReadFCvtF32ToF16, 0>;
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def : ReadAdvance<ReadFCvtI32ToF16, 0>;
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def : ReadAdvance<ReadFCvtF16ToI64, 0>;
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def : ReadAdvance<ReadFCvtF16ToF32, 0>;
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def : ReadAdvance<ReadFCvtF16ToI32, 0>;
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def : ReadAdvance<ReadFDiv16, 0>;
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def : ReadAdvance<ReadFCmp16, 0>;
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def : ReadAdvance<ReadFMA16, 0>;
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def : ReadAdvance<ReadFMinMax16, 0>;
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def : ReadAdvance<ReadFMul16, 0>;
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def : ReadAdvance<ReadFMovI16ToF16, 0>;
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def : ReadAdvance<ReadFMovF16ToI16, 0>;
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def : ReadAdvance<ReadFSGNJ16, 0>;
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def : ReadAdvance<ReadFSqrt16, 0>;
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} // Unsupported = true
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}
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multiclass UnsupportedSchedSFB {
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let Unsupported = true in {
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def : WriteRes<WriteSFB, []>;
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def : ReadAdvance<ReadSFBJmp, 0>;
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def : ReadAdvance<ReadSFBALU, 0>;
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} // Unsupported = true
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}
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multiclass UnsupportedSchedZfa {
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let Unsupported = true in {
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def : WriteRes<WriteFRoundF16, []>;
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def : WriteRes<WriteFRoundF32, []>;
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def : WriteRes<WriteFRoundF64, []>;
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def : WriteRes<WriteFLI16, []>;
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def : WriteRes<WriteFLI32, []>;
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def : WriteRes<WriteFLI64, []>;
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def : ReadAdvance<ReadFRoundF32, 0>;
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def : ReadAdvance<ReadFRoundF64, 0>;
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def : ReadAdvance<ReadFRoundF16, 0>;
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} // Unsupported = true
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}
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multiclass UnsupportedSchedZabha {
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let Unsupported = true in {
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def : WriteRes<WriteAtomicB, []>;
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def : WriteRes<WriteAtomicH, []>;
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def : ReadAdvance<ReadAtomicBA, 0>;
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def : ReadAdvance<ReadAtomicBD, 0>;
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def : ReadAdvance<ReadAtomicHA, 0>;
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def : ReadAdvance<ReadAtomicHD, 0>;
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} // Unsupported = true
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}
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// Include the scheduler resources for other instruction extensions.
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include "RISCVScheduleZb.td"
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include "RISCVScheduleV.td"
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include "RISCVScheduleXSf.td"
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