llvm-project

AsmParser

[RISCV] Check that the stack adjust immediate for cm.push/pop* has the correct sign and is divisible by 16. (#85295 )

2024-03-26 13:31:21 -07:00

Disassembler

[RISCV] Add back SiFive's cdiscard.d.l1, cflush.d.l1, and cease instructions. (#83896 )

2024-03-13 14:56:25 -07:00

GISel

Recommit [RISCV] RISCV vector calling convention (2/2) (#79096 ) (#87736 )

2024-04-16 19:59:36 +08:00

MCA

[RISCV] Add TargetParser to MCA (#84109 )

2024-03-06 11:49:28 +08:00

MCTargetDesc

[RISCV] Add validation of SPIMM for cm.push/pop. (#84989 )

2024-03-28 08:38:18 -07:00

TargetInfo

…

CMakeLists.txt

[CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (#77770 )

2024-02-26 12:12:31 +00:00

RISCV.h

[CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (#77770 )

2024-02-26 12:12:31 +00:00

RISCV.td

[RISCV] Move the RISCVSchedule.td include after RISCVRegisterInfo.td. NFC

2024-03-22 11:42:12 -07:00

RISCVAsmPrinter.cpp

[RISCV] Implement Statepoint and Patchpoint lowering to call instructions (#77337 )

2024-04-11 12:19:56 +08:00

RISCVCallingConv.td

[RISCV] RISCV vector calling convention (1/2) (#77560 )

2024-03-27 23:03:13 +08:00

RISCVCodeGenPrepare.cpp

[RISCV] Don't look for sext in RISCVCodeGenPrepare::visitAnd.

2024-01-19 14:44:47 -08:00

RISCVCombine.td

[RISCV][GISel] Add a post legalizer combiner and enable a couple comb… (#67053 )

2023-09-22 10:13:56 -07:00

RISCVDeadRegisterDefinitions.cpp

[RISCV] Cleanup pass initialization.

2023-12-07 18:21:38 -08:00

RISCVExpandAtomicPseudoInsts.cpp

[RISCV] Prevent tryToFoldBNEOnCmpXchgResult from deleting AND if it has others users.

2023-08-28 10:11:12 -07:00

RISCVExpandPseudoInsts.cpp

[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954 )

2024-04-16 15:40:32 -07:00

RISCVFeatures.td

[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954 )

2024-04-16 15:40:32 -07:00

RISCVFoldMasks.cpp

[RISCV] Use DenseMap to track V0 definition. NFC (#84465 )

2024-03-21 15:38:43 +08:00

RISCVFrameLowering.cpp

[RISCV] Add CFI information for vector callee-saved registers (#86811 )

2024-04-17 10:42:40 +08:00

RISCVFrameLowering.h

[RISCV] Add CFI information for vector callee-saved registers (#86811 )

2024-04-17 10:42:40 +08:00

RISCVGatherScatterLowering.cpp

[NFC][RemoveDIs] Use iterators for insertion at various call-sites (#84736 )

2024-03-19 16:36:29 +00:00

RISCVGISel.td

[RISCV][GISel] Support G_ROTL/G_ROTR with Zbb. (#72825 )

2023-12-04 13:00:34 -08:00

RISCVInsertReadWriteCSR.cpp

[RISCV] Implement foward inserting save/restore FRM instructions. (#77744 )

2024-01-25 14:41:52 +08:00

RISCVInsertVSETVLI.cpp

[RISCV] Convert VTYPE operand check to assert in RISCVInsertVSETVLI. NFC

2024-04-17 10:11:03 +08:00

RISCVInsertWriteVXRM.cpp

[RISCV] Don't emit vxrm writes for vnclip(u).wi with shift of 0. (#76578 )

2024-01-02 09:50:06 -08:00

RISCVInstrFormats.td

[RISCV] Rename OP-P to OP-VE. (#87546 )

2024-04-05 17:02:03 -07:00

RISCVInstrFormatsC.td

[RISCV] Remove unused Opcode field from RVInst16. NFC

2023-07-20 08:18:06 -07:00

RISCVInstrFormatsV.td

[RISCV] Remove Opcode field from RVInst. Assign Inst{6-0} directly. NFC

2023-07-20 08:18:06 -07:00

RISCVInstrGISel.td

[RISCV][GISEL] Legalize G_ZEXT, G_SEXT, and G_ANYEXT, G_SPLAT_VECTOR, and G_ICMP for scalable vector types

2024-04-03 15:27:15 -07:00

RISCVInstrInfo.cpp

[RISCV] Fix obvious copy paste error.

2024-04-16 16:32:57 +01:00

RISCVInstrInfo.h

[MachineCombiner][NFC] Split target-dependent patterns

2024-04-11 12:20:27 +08:00

RISCVInstrInfo.td

[RISCV] Give HWASAN_CHECK_MEMACCESS_SHORTGRANULES pseudo the same code size as PseudoCall.

2024-04-11 17:13:51 -07:00

RISCVInstrInfoA.td

[RISCV] Remove mayLoad = 1 from store-conditional (#88470 )

2024-04-12 08:45:47 -07:00

RISCVInstrInfoC.td

[RISCV] Fix scheduling info for compressed LD/ST of FP types. (#82339 )

2024-02-21 08:47:39 +01:00

RISCVInstrInfoD.td

[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887 )

2024-03-20 08:44:24 -07:00

RISCVInstrInfoF.td

[RISCV] Add casts to isel patterns that produce more than 1 instruction.

2024-02-08 23:38:19 -08:00

RISCVInstrInfoM.td

[RISCV] Split div vs rem scheduling information [nfc] (#84385 )

2024-03-07 14:03:58 -08:00

RISCVInstrInfoSFB.td

[RISCV][NFC] Move SFB pseudos and patterns to RISCVInstrInfoSFB.td (#80945 )

2024-02-07 16:03:30 +08:00

RISCVInstrInfoV.td

[RISCV] Model vd as a src for some Zvk* instructions in MC layer. (#86710 )

2024-03-27 12:20:24 -07:00

RISCVInstrInfoVPseudos.td

[RISCV] Make more vector pseudos commutable

2024-04-16 15:55:14 +08:00

RISCVInstrInfoVSDPatterns.td

[RISCV] Split PseudoVFMIN, PseudoVFMAX PseudoVFSGNJ, PseudoVFSGNJN, and PseudoVFSGNJX by SEW

2024-04-15 06:09:14 -07:00

RISCVInstrInfoVVLPatterns.td

[RISCV] Split PseudoVFMIN, PseudoVFMAX PseudoVFSGNJ, PseudoVFSGNJN, and PseudoVFSGNJX by SEW

2024-04-15 06:09:14 -07:00

RISCVInstrInfoXCV.td

[RISCV] Implement intrinsics for XCVbitmanip extension in CV32E40P (#74993 )

2023-12-17 19:29:40 +08:00

RISCVInstrInfoXSf.td

[RISCV] Add scheduling information for SiFive VCIX (#86093 )

2024-04-16 13:55:45 +08:00

RISCVInstrInfoXTHead.td

[RISCV] Add casts to isel patterns that produce more than 1 instruction.

2024-02-08 23:38:19 -08:00

RISCVInstrInfoXVentana.td

[RISCV] Rename Ventana DecoderNamespace to XVentana for matching other extension. NFC.

2023-08-19 12:44:59 +08:00

RISCVInstrInfoZa.td

[RISCV][ISel] Add codegen support for the experimental zabha extension (#80192 )

2024-02-16 15:35:09 +08:00

RISCVInstrInfoZalasr.td

[RISCV][MC] MC layer support for the experimental zalasr extension (#79911 )

2024-02-01 10:58:21 -08:00

RISCVInstrInfoZb.td

[RISCV] Extend pattern matches involving shNadd to support disjoint or (#87001 )

2024-03-28 16:34:04 -07:00

RISCVInstrInfoZc.td

[RISCV] Add validation of SPIMM for cm.push/pop. (#84989 )

2024-03-28 08:38:18 -07:00

RISCVInstrInfoZcmop.td

[RISCV] Correct the spelling of the Zcmop mnemonics. (#88826 )

2024-04-15 22:33:14 -07:00

RISCVInstrInfoZfa.td

[RISCV] Apply IsSignExtendingOpW = 1 on fcvtmod.w.d (#69633 )

2023-10-19 14:55:33 -07:00

RISCVInstrInfoZfbfmin.td

[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357 )

2023-11-01 09:36:41 -07:00

RISCVInstrInfoZfh.td

[RISCV] Add casts to isel patterns that produce more than 1 instruction.

2024-02-08 23:38:19 -08:00

RISCVInstrInfoZicbo.td

[RISCV] Match prefetch address with offset (#66072 )

2023-10-20 14:22:48 +08:00

RISCVInstrInfoZicfiss.td

[RISCV] Add MC layer support for Zicfiss. (#66043 )

2023-12-30 15:40:20 +08:00

RISCVInstrInfoZicond.td

[RISCV] Graduate Zicond to non-experimental (#79811 )

2024-01-29 15:58:54 +00:00

RISCVInstrInfoZimop.td

[RISCV] Zimop/Zcmop are ratified

2024-04-08 16:40:02 +08:00

RISCVInstrInfoZk.td

[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472 )

2023-10-08 14:13:08 +08:00

RISCVInstrInfoZvfbf.td

[RISCV] Model all 3 arithmetic sources of vector FMA at MC layer.

2023-08-04 09:08:16 -07:00

RISCVInstrInfoZvk.td

[RISCV] Add missing space to RISCVInstrInfoZvk.td. NFC

2024-04-15 12:45:06 -07:00

RISCVISelDAGToDAG.cpp

[RISCV] Add patterns for fixed vector vwsll (#87316 )

2024-04-04 11:30:23 +08:00

RISCVISelDAGToDAG.h

[RISCV][SiFive] Reduce intrinsics of SiFive VCIX extension (#79407 )

2024-01-26 11:15:53 +08:00

RISCVISelLowering.cpp

[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954 )

2024-04-16 15:40:32 -07:00

RISCVISelLowering.h

Recommit [RISCV] RISCV vector calling convention (2/2) (#79096 ) (#87736 )

2024-04-16 19:59:36 +08:00

RISCVMachineFunctionInfo.cpp

…

RISCVMachineFunctionInfo.h

[RISCV] Fix wrong offset use caused by missing the size of Zcmp push. (#66613 )

2023-09-25 12:05:05 +08:00

RISCVMacroFusion.td

[RISCV] Use TableGen-based macro fusion (#72224 )

2024-01-25 17:10:49 +08:00

RISCVMakeCompressible.cpp

[RISCV] Teach RISCVMakeCompressible handle byte/half load/store for Zcb. (#83375 )

2024-03-27 13:40:38 +08:00

RISCVMergeBaseOffset.cpp

[RISCV] Merge ADDI with X0 into base offset (#78940 )

2024-01-23 09:57:05 +08:00

RISCVMoveMerger.cpp

[RISCV] Cleanup pass initialization.

2023-12-07 18:21:38 -08:00

RISCVOptWInstrs.cpp

[RISCV] Generate more W instructons

2024-04-16 15:37:31 +08:00

RISCVPostRAExpandPseudoInsts.cpp

[RISCV][NFC] Pass MCSubtargetInfo instead of FeatureBitset in RISCVMatInt (#71770 )

2023-11-09 15:15:23 +08:00

RISCVProcessors.td

[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954 )

2024-04-16 15:40:32 -07:00

RISCVPushPopOptimizer.cpp

[RISCV] Add correct Uses, Defs, isReturn to Zcmp (#81039 )

2024-02-07 14:30:45 -08:00

RISCVRedundantCopyElimination.cpp

…

RISCVRegisterInfo.cpp

[RISCV] Address review comment from 88062

2024-04-10 07:21:41 -07:00

RISCVRegisterInfo.h

[RISCV] Store VLMul/NF into RegisterClass's TSFlags

2024-04-08 13:35:37 +08:00

RISCVRegisterInfo.td

[RISCV] Store VLMul/NF into RegisterClass's TSFlags

2024-04-08 13:35:37 +08:00

RISCVSchedRocket.td

[RISCV] Add scheduling information for SiFive VCIX (#86093 )

2024-04-16 13:55:45 +08:00

RISCVSchedSiFive7.td

[RISCV] Add scheduling information for SiFive VCIX (#86093 )

2024-04-16 13:55:45 +08:00

RISCVSchedSiFiveP400.td

[RISCV] Add scheduling information for SiFive VCIX (#86093 )

2024-04-16 13:55:45 +08:00

RISCVSchedSiFiveP600.td

[RISCV] Add scheduling information for SiFive VCIX (#86093 )

2024-04-16 13:55:45 +08:00

RISCVSchedSyntacoreSCR1.td

[RISCV] Add scheduling information for SiFive VCIX (#86093 )

2024-04-16 13:55:45 +08:00

RISCVSchedule.td

[RISCV] Add scheduling information for SiFive VCIX (#86093 )

2024-04-16 13:55:45 +08:00

RISCVScheduleV.td

[RISCV] Split PseudoVFMIN, PseudoVFMAX PseudoVFSGNJ, PseudoVFSGNJN, and PseudoVFSGNJX by SEW

2024-04-15 06:09:14 -07:00

RISCVScheduleXSf.td

[RISCV] Add scheduling information for SiFive VCIX (#86093 )

2024-04-16 13:55:45 +08:00

RISCVScheduleZb.td

[RISCV] Add sched classes for Zbb integer min max instructions

2024-03-14 06:02:42 -07:00

RISCVSchedXiangShanNanHu.td

[RISCV] Add scheduling information for SiFive VCIX (#86093 )

2024-04-16 13:55:45 +08:00

RISCVSubtarget.cpp

[RISCV] Use TableGen-based macro fusion (#72224 )

2024-01-25 17:10:49 +08:00

RISCVSubtarget.h

[RISCV][NFC] Add isTargetAndroid API in RISCVSubtarget (#87671 )

2024-04-04 15:21:59 -07:00

RISCVSystemOperands.td

[RISCV] Add the CSR names from Smrnmi. (#83370 )

2024-03-19 21:27:25 -07:00

RISCVTargetMachine.cpp

[RISCV][NFC] Add helpers for RVV register classes

2024-03-07 14:18:37 +08:00

RISCVTargetMachine.h

[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295 )

2023-09-14 14:10:14 -07:00

RISCVTargetObjectFile.cpp

[RISCV] Place mergeable small read only data into srodata section (#82214 )

2024-03-11 13:57:06 +08:00

RISCVTargetObjectFile.h

[RISCV] Place mergeable small read only data into srodata section (#82214 )

2024-03-11 13:57:06 +08:00

RISCVTargetTransformInfo.cpp

[RISCV][TTI] Scale the cost of ICmp with LMUL (#88235 )

2024-04-16 09:37:32 +08:00

RISCVTargetTransformInfo.h

[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954 )

2024-04-16 15:40:32 -07:00