ShihPo Hung 2be906b255 Revert "[TTI][RISCV] Add cost modelling for intrinsic vp.load.ff (#160470)" ...

This reverts commit aa08b1a9963f33ded658d3ee655429e1121b5212.

2025-09-26 17:24:56 -07:00

..

AArch64

[AArch64] Give a higher cost for more expensive SVE FCMP instructions (#153816)

2025-09-04 19:50:39 +01:00

AMDGPU

[AMDGPU] Fix vector legalization for bf16 valu ops (#158439)

2025-09-25 10:07:11 +01:00

ARM

[ARM] Replace ABS and tABS machine nodes with custom lowering (#156717)

2025-09-19 19:43:36 +01:00

NVPTX

[NVPTX] Improve modeling of inline PTX (#130675)

2025-03-25 13:46:16 -07:00

PowerPC

[PowerPC] Update data layout aligment of i128 to 16 (#118004)

2024-12-09 18:02:24 -05:00

RISCV

Revert "[TTI][RISCV] Add cost modelling for intrinsic vp.load.ff (#160470)"

2025-09-26 17:24:56 -07:00

SystemZ

[IR] Remove size argument from lifetime intrinsics (#150248)

2025-08-08 11:09:34 +02:00

X86

[CostModel][X86] Add missing AVX1 costs for PMULUDQ v4i64 pattern (#157475)

2025-09-08 15:06:33 +00:00

free-intrinsics-datalayout.ll

[IR] Remove size argument from lifetime intrinsics (#150248)

2025-08-08 11:09:34 +02:00

free-intrinsics-no_info.ll

[IR] Remove size argument from lifetime intrinsics (#150248)

2025-08-08 11:09:34 +02:00

no_info.ll

…