Sander de Smalen 0fe9453005 [AArch64][SME] Make all SME intrinsics use 32bit immediates.
This aligns with what was done for SVE, which consistently uses 32bit
immediates at the LLVM IR level.

Additionally, this change forces the intrinsic operands to be immediates
using ImmArg<>, which subsequently requires the codegenerator to match
TargetConstants instead of Constants.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D136933
2022-10-31 11:28:12 +00:00
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++ SVE CodeGen Warnings ++

When the WARN check lines fail in the SVE codegen tests it most likely means you
have introduced a warning due to:
1. Adding an invalid call to VectorType::getNumElements() or EVT::getVectorNumElements()
   when the type is a scalable vector.
2. Relying upon an implicit cast conversion from TypeSize to uint64_t.

For generic code, please modify your code to work with ElementCount and TypeSize directly.
For target-specific code that only deals with fixed-width vectors, use the fixed-size interfaces.
Please refer to the code where those functions live for more details.