Craig Topper 8ba2ae31fa

[RISCV][GISel] Implement canLowerReturn. (#105465) ...

This allows us to handle return values that are too large to fit in x10
and x11. They will be converted to a sret by passing a pointer to where
to store the return value.

2024-08-22 08:12:51 -07:00

..

AsmParser

[RISCV] Remove unused tablegen classes from unratified Zbp instructions. NFC

2024-08-17 23:41:18 -07:00

Disassembler

[RISCV] Add QingKe "XW" compressed opcode extension (#97925)

2024-07-11 11:10:02 +08:00

GISel

[RISCV][GISel] Implement canLowerReturn. (#105465)

2024-08-22 08:12:51 -07:00

MCA

[RISCV][NFC] Include RISCVVInversePseudosTable in RISCVMCTargetDesc

2024-04-24 09:29:20 -07:00

MCTargetDesc

[NFC] Eliminate top-level "using namespace" from some headers. (#102751)

2024-08-11 13:10:48 -07:00

TargetInfo

…

CMakeLists.txt

[RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (#91860)

2024-08-08 13:22:59 +08:00

RISCV.h

[RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (#91860)

2024-08-08 13:22:59 +08:00

RISCV.td

[RISCV] Add scheduling model for Syntacore SCR4 and SCR5 (#102909)

2024-08-14 11:42:31 +03:00

RISCVAsmPrinter.cpp

[RISCV] Rename merge operand -> passthru. NFC (#100330)

2024-07-30 17:47:00 +08:00

RISCVCallingConv.td

[RISCV] RISCV vector calling convention (1/2) (#77560)

2024-03-27 23:03:13 +08:00

RISCVCodeGenPrepare.cpp

[RISCV] Use experimental.vp.splat to splat specific vector length elements. (#101329)

2024-08-01 09:37:42 +08:00

RISCVCombine.td

…

RISCVDeadRegisterDefinitions.cpp

[CodeGen][NewPM] Port LiveIntervals to new pass manager (#98118)

2024-07-10 19:34:48 +08:00

RISCVExpandAtomicPseudoInsts.cpp

…

RISCVExpandPseudoInsts.cpp

[RISCV] Move PseudoVSET(I)VLI expansion to use PseudoInstExpansion. (#102496)

2024-08-09 11:47:06 -07:00

RISCVFeatures.td

[RISCV] Add CSRs and an instruction for Smctr and Ssctr extensions. (#105148)

2024-08-21 19:23:07 -07:00

RISCVFrameLowering.cpp

[RISCV][CFI] Emit cfi_offset for every callee-saved vector registers (#100455)

2024-07-29 11:03:07 +08:00

RISCVFrameLowering.h

[RISCV] Add CFI information for vector callee-saved registers (#86811)

2024-04-17 10:42:40 +08:00

RISCVGatherScatterLowering.cpp

[llvm] Make InstSimplifyFolder constructor explicit (NFC) (#101654)

2024-08-02 16:45:50 +03:00

RISCVGISel.td

[RISCV][GISel] Move i32 patterns that aren't used by SelectionDAG to RISCVGISel.td. NFC (#102685)

2024-08-12 09:34:02 -07:00

RISCVIndirectBranchTracking.cpp

[RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (#91860)

2024-08-08 13:22:59 +08:00

RISCVInsertReadWriteCSR.cpp

[CodeGen] Make the parameter TRI required in some functions. (#85968)

2024-04-24 14:24:14 +01:00

RISCVInsertVSETVLI.cpp

[RISCV] Rename merge operand -> passthru. NFC (#100330)

2024-07-30 17:47:00 +08:00

RISCVInsertWriteVXRM.cpp

[CodeGen] Make the parameter TRI required in some functions. (#85968)

2024-04-24 14:24:14 +01:00

RISCVInstrFormats.td

[RISCV] Move ActiveElementsAffectResult to TSFlags. NFC (#101123)

2024-08-05 12:08:03 +08:00

RISCVInstrFormatsC.td

…

RISCVInstrFormatsV.td

…

RISCVInstrGISel.td

[RISCV][GISEL] Legalize G_ZEXT, G_SEXT, and G_ANYEXT, G_SPLAT_VECTOR, and G_ICMP for scalable vector types

2024-04-03 15:27:15 -07:00

RISCVInstrInfo.cpp

[RISCV] Increase default tail duplication threshold to 6 at -O3 (#98873)

2024-08-01 12:24:25 +08:00

RISCVInstrInfo.h

[RISCV] Move ActiveElementsAffectResult to TSFlags. NFC (#101123)

2024-08-05 12:08:03 +08:00

RISCVInstrInfo.td

[RISCV] Add CSRs and an instruction for Smctr and Ssctr extensions. (#105148)

2024-08-21 19:23:07 -07:00

RISCVInstrInfoA.td

[RISCV][GISel] Move i32 patterns that aren't used by SelectionDAG to RISCVGISel.td. NFC (#102685)

2024-08-12 09:34:02 -07:00

RISCVInstrInfoC.td

[RISCV] Fix InsnCI register type (#100113)

2024-07-23 21:19:57 +08:00

RISCVInstrInfoD.td

RISC-V: Add fminimumnum and fmaximumnum support (#104411)

2024-08-21 09:10:55 +08:00

RISCVInstrInfoF.td

RISC-V: Add fminimumnum and fmaximumnum support (#104411)

2024-08-21 09:10:55 +08:00

RISCVInstrInfoM.td

[RISCV][GISel] Move i32 patterns that aren't used by SelectionDAG to RISCVGISel.td. NFC (#102685)

2024-08-12 09:34:02 -07:00

RISCVInstrInfoSFB.td

…

RISCVInstrInfoV.td

[RISCV] Move ActiveElementsAffectResult to TSFlags. NFC (#101123)

2024-08-05 12:08:03 +08:00

RISCVInstrInfoVPseudos.td

[RISCV] Use getAllOnesConstant/getSignedConstant.

2024-08-17 00:18:41 -07:00

RISCVInstrInfoVSDPatterns.td

[RISCV] Rename hasVInstructionsBF16 to hasVInstructionsBF16Minimal. NFC (#101080)

2024-07-29 21:55:42 -07:00

RISCVInstrInfoVVLPatterns.td

[RISCV] Add back missing vmv_v_x_vl pattern predicates (#101455)

2024-08-01 15:25:36 +08:00

RISCVInstrInfoXCV.td

[RISCV] Implement Intrinsics for XCVmac Extension in CV32E40P (#83112)

2024-07-15 10:25:25 +10:00

RISCVInstrInfoXSf.td

[RISCV] Move ActiveElementsAffectResult to TSFlags. NFC (#101123)

2024-08-05 12:08:03 +08:00

RISCVInstrInfoXTHead.td

[RISCV][GISel] Move i32 patterns that aren't used by SelectionDAG to RISCVGISel.td. NFC (#102685)

2024-08-12 09:34:02 -07:00

RISCVInstrInfoXVentana.td

[RISCV] Remove IsRV64 from XVentanaCondOps patterns. (#100891)

2024-07-27 17:26:32 -07:00

RISCVInstrInfoXwch.td

[RISCV] Add QingKe "XW" compressed opcode extension (#97925)

2024-07-11 11:10:02 +08:00

RISCVInstrInfoZa.td

DAG: Replace bitwidth with type in suffix in atomic tablegen ops (#94845)

2024-06-13 11:52:22 +02:00

RISCVInstrInfoZalasr.td

…

RISCVInstrInfoZb.td

[RISCV] Improve BCLRITwoBitsMaskHigh SDNodeXForm. NFC

2024-08-19 10:32:47 -07:00

RISCVInstrInfoZc.td

[RISCV] Make M imply Zmmul (#95070)

2024-06-21 11:11:10 +08:00

RISCVInstrInfoZcmop.td

[RISCV] Correct the spelling of the Zcmop mnemonics. (#88826)

2024-04-15 22:33:14 -07:00

RISCVInstrInfoZfa.td

…

RISCVInstrInfoZfbfmin.td

…

RISCVInstrInfoZfh.td

RISC-V: Add fminimumnum and fmaximumnum support (#104411)

2024-08-21 09:10:55 +08:00

RISCVInstrInfoZicbo.td

…

RISCVInstrInfoZicfiss.td

…

RISCVInstrInfoZicond.td

…

RISCVInstrInfoZimop.td

[RISCV] Zimop/Zcmop are ratified

2024-04-08 16:40:02 +08:00

RISCVInstrInfoZk.td

…

RISCVInstrInfoZvfbf.td

…

RISCVInstrInfoZvk.td

[RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (#103709)

2024-08-19 11:50:32 +08:00

RISCVISelDAGToDAG.cpp

[RISCV] Add isel optimization for (and (sra y, c2), c1) to recover regression from #101751. (#104114)

2024-08-20 09:41:46 -07:00

RISCVISelDAGToDAG.h

[RISCV] Codegen support for XCVmem extension (#76916)

2024-06-07 21:45:49 +08:00

RISCVISelLowering.cpp

[RISCV] Minor style fixes in lowerVectorMaskVecReduction [nfc]

2024-08-21 10:47:17 -07:00

RISCVISelLowering.h

[IA][AArch64]: Construct (de)interleave4 out of (de)interleave2 (#89276)

2024-08-12 17:23:00 +01:00

RISCVLandingPadSetup.cpp

[RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (#91860)

2024-08-08 13:22:59 +08:00

RISCVMachineFunctionInfo.cpp

…

RISCVMachineFunctionInfo.h

[llvm-project] Fix typo "seperate" (#95373)

2024-06-13 20:20:27 +01:00

RISCVMacroFusion.td

…

RISCVMakeCompressible.cpp

[RISCV] Teach RISCVMakeCompressible handle byte/half load/store for Zcb. (#83375)

2024-03-27 13:40:38 +08:00

RISCVMergeBaseOffset.cpp

[RISCV] Don't crash in RISCVMergeBaseOffset if INLINE_ASM uses address register in a non-memory constraint. (#100790)

2024-07-26 17:11:01 -07:00

RISCVMoveMerger.cpp

…

RISCVOptWInstrs.cpp

[RISCV] Add some Zfinx instructions to hasAllNBitUsers.

2024-08-08 17:33:54 -07:00

RISCVPostRAExpandPseudoInsts.cpp

[RISCV] Remove unneeded code from RISCVPostRAExpandPseudo::expandMovImm. NFC

2024-06-27 18:42:27 -07:00

RISCVProcessors.td

[RISCV] Add Hazard3 Core as taped out for RP2350 (#102452)

2024-08-21 08:45:45 +01:00

RISCVProfiles.td

[RISCV] Use listconcat to shorten some of the profile feature lists. (#102356)

2024-08-08 09:15:43 -07:00

RISCVPushPopOptimizer.cpp

…

RISCVRedundantCopyElimination.cpp

[RISCV] Codegen support for XCVbi extension (#89719)

2024-05-08 11:22:16 +08:00

RISCVRegisterInfo.cpp

[RISCV] Mark all registers marked isConstant as reserved (#96002)

2024-06-23 15:44:41 -07:00

RISCVRegisterInfo.h

[RISCV] Store VLMul/NF into RegisterClass's TSFlags

2024-04-08 13:35:37 +08:00

RISCVRegisterInfo.td

[RISCV] Use software guarded branch for indirect jump table branch. (#66762)

2024-05-14 14:44:25 +08:00

RISCVSchedRocket.td

[RISCV] Add Sched classes for vector crypto instructions (#90068)

2024-05-03 11:11:29 -04:00

RISCVSchedSiFive7.td

[RISCV] Rename merge operand -> passthru. NFC (#100330)

2024-07-30 17:47:00 +08:00

RISCVSchedSiFiveP400.td

[RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (#102155)

2024-08-19 09:41:42 -04:00

RISCVSchedSiFiveP600.td

[RISCV] Rename merge operand -> passthru. NFC (#100330)

2024-07-30 17:47:00 +08:00

RISCVSchedSyntacoreSCR1.td

[RISCV][NFC] Cleanup SCR1 sched model (#96088)

2024-06-20 18:14:09 +03:00

RISCVSchedSyntacoreSCR345.td

[RISCV] Add scheduling model for Syntacore SCR4 and SCR5 (#102909)

2024-08-14 11:42:31 +03:00

RISCVSchedule.td

[RISCV][NFC] Add UnsupportedSched<F|D|A> multiclasses (#95948)

2024-06-19 12:37:47 +03:00

RISCVScheduleV.td

[RISCV] Rename merge operand -> passthru. NFC (#100330)

2024-07-30 17:47:00 +08:00

RISCVScheduleXSf.td

[RISCV] Add scheduling information for SiFive VCIX (#86093)

2024-04-16 13:55:45 +08:00

RISCVScheduleZb.td

[RISCV] Add sched classes for Zbb integer min max instructions

2024-03-14 06:02:42 -07:00

RISCVScheduleZvk.td

[RISCV] Add Sched classes for vector crypto instructions (#90068)

2024-05-03 11:11:29 -04:00

RISCVSchedXiangShanNanHu.td

[RISCV] Add Sched classes for vector crypto instructions (#90068)

2024-05-03 11:11:29 -04:00

RISCVSubtarget.cpp

[RISCV] Disable fixed length vectors with Zve32* without Zvl64b. (#102405)

2024-08-08 09:17:43 -07:00

RISCVSubtarget.h

[RISCV] Increase default tail duplication threshold to 6 at -O3 (#98873)

2024-08-01 12:24:25 +08:00

RISCVSystemOperands.td

[RISCV] Add CSRs and an instruction for Smctr and Ssctr extensions. (#105148)

2024-08-21 19:23:07 -07:00

RISCVTargetMachine.cpp

[LSR] Split the -lsr-term-fold transformation into it's own pass (#104234)

2024-08-17 18:34:23 -07:00

RISCVTargetMachine.h

[RISCV][LoopIdiomVectorize] Support VP intrinsics in LoopIdiomVectorize (#94082)

2024-07-02 18:48:28 -07:00

RISCVTargetObjectFile.cpp

[IR] Don't include Module.h in Analysis.h (NFC) (#97023)

2024-06-28 14:30:47 +02:00

RISCVTargetObjectFile.h

[Driver] Default -msmall-data-limit= to 0 and clean up code

2024-08-19 18:20:02 -07:00

RISCVTargetTransformInfo.cpp

[RISCV] Implement RISCVTTIImpl::shouldConsiderAddressTypePromotion for RISCV (#102560)

2024-08-15 10:37:04 +08:00

RISCVTargetTransformInfo.h

[LSR] Split the -lsr-term-fold transformation into it's own pass (#104234)

2024-08-17 18:34:23 -07:00

RISCVVectorPeephole.cpp

[RISCV] Introduce local peephole to reduce VLs based on demanded VL (#104689)

2024-08-22 07:34:41 -07:00