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llvm-project/llvm/lib/Target/RISCV
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Shao-Ce SUN 005fd8aa70 [RISCV] Add support for Zihintpause extention 
Add support for the 'pause' hint instruction as an alias for
'fence w, 0'. To do this allow the 'fence' operands pred and succ
to be set to 0 (the empty set). This will also allow future hints
to be encoded as 'fence 0, <x>' and 'fence <x>, 0'.

This patch revised from @mundaym's D93019.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D117789
2022-02-03 20:55:47 +08:00
..
AsmParser
[RISCV] Add support for Zihintpause extention
2022-02-03 20:55:47 +08:00
Disassembler
…
MCTargetDesc
[RISCV] Add support for Zihintpause extention
2022-02-03 20:55:47 +08:00
TargetInfo
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CMakeLists.txt
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RISCV.h
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RISCV.td
[RISCV] Add support for Zihintpause extention
2022-02-03 20:55:47 +08:00
RISCVAsmPrinter.cpp
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RISCVCallingConv.td
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RISCVCallLowering.cpp
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RISCVCallLowering.h
…
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes.
2022-01-28 09:51:49 -08:00
RISCVExpandPseudoInsts.cpp
[RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes.
2022-01-28 09:51:49 -08:00
RISCVFrameLowering.cpp
[RISCV] Fix the bug in the register allocator caused by reserved BP.
2022-01-21 01:23:01 +00:00
RISCVFrameLowering.h
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RISCVGatherScatterLowering.cpp
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RISCVInsertVSETVLI.cpp
[RISCC] Add missing words to comment. NFC
2022-02-01 07:39:51 -08:00
RISCVInstrFormats.td
[RISCV] Add strictfp support for compares.
2022-01-11 20:01:41 -08:00
RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td
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RISCVInstrInfo.cpp
[RISCV] Use tablegen size for getInstSizeInBytes.
2022-01-28 09:21:28 -08:00
RISCVInstrInfo.h
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RISCVInstrInfo.td
[RISCV] Add support for Zihintpause extention
2022-02-03 20:55:47 +08:00
RISCVInstrInfoA.td
[RISCV] Use tablegen size for getInstSizeInBytes.
2022-01-28 09:21:28 -08:00
RISCVInstrInfoC.td
…
RISCVInstrInfoD.td
[RISCV] Optimize lowering of floating-point -0.0
2022-01-20 11:46:28 +00:00
RISCVInstrInfoF.td
[RISCV] Optimize lowering of floating-point -0.0
2022-01-20 11:46:28 +00:00
RISCVInstrInfoM.td
…
RISCVInstrInfoV.td
[RISCV] Remove Zvlsseg extension.
2022-01-20 12:40:07 -08:00
RISCVInstrInfoVPseudos.td
[RISCV] Use tablegen size for getInstSizeInBytes.
2022-01-28 09:21:28 -08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Prefer vmslt.vx v0, v8, zero over vmsle.vi v0, v8, -1.
2022-01-27 11:48:27 -08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Add DAG combines to transform ADD_VL/SUB_VL into widening add/sub.
2022-02-02 10:03:08 -08:00
RISCVInstrInfoZb.td
[RISCV] Lower riscv_zip/unzip intrinsic to RISCVISD::SHFL/UNSHFL.
2022-01-30 13:27:41 -08:00
RISCVInstrInfoZfh.td
[RISCV] Separate the Zfhmin and Zfh extensions.
2022-01-31 09:06:43 -08:00
RISCVInstrInfoZk.td
[RISCV] Adjust some comments.
2022-02-01 22:53:54 +08:00
RISCVInstructionSelector.cpp
…
RISCVISelDAGToDAG.cpp
[RISCV] Cleanup some places that assumed VLMaxSentinel and -1 constant mean the same thing. NFCI
2022-02-02 12:23:12 -08:00
RISCVISelDAGToDAG.h
[RISCV] Add the passthru operand for RVV nomask load intrinsics.
2022-01-25 17:31:36 -08:00
RISCVISelLowering.cpp
[RISCV] Remove unused variables. NFC
2022-02-02 19:23:16 -08:00
RISCVISelLowering.h
[RISCV] Add DAG combines to transform ADD_VL/SUB_VL into widening add/sub.
2022-02-02 10:03:08 -08:00
RISCVLegalizerInfo.cpp
…
RISCVLegalizerInfo.h
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RISCVMachineFunctionInfo.h
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RISCVMCInstLower.cpp
[NFC] Use Register instead of unsigned
2022-01-19 20:17:04 +08:00
RISCVMergeBaseOffset.cpp
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RISCVRegisterBankInfo.cpp
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RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
RISCVRegisterInfo.h
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
RISCVRegisterInfo.td
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
RISCVSchedRocket.td
[RISCV] add support for zbkx subextension in MC layer.
2022-01-24 20:38:46 +08:00
RISCVSchedSiFive7.td
[RISCV] add support for zbkx subextension in MC layer.
2022-01-24 20:38:46 +08:00
RISCVSchedule.td
…
RISCVScheduleB.td
[RISCV] Add instruction schedule for Zbc extension and Zbs extension
2022-01-18 07:31:50 +00:00
RISCVScheduleV.td
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RISCVSExtWRemoval.cpp
[RISCV][NFC] Make Zb* instruction naming match the convention used elsewhere in the RISC-V backend
2022-01-28 15:20:37 +00:00
RISCVSubtarget.cpp
[RISCV] Fix support of vlen = 64.
2022-01-26 16:31:21 +08:00
RISCVSubtarget.h
[RISCV] Add support for Zihintpause extention
2022-02-03 20:55:47 +08:00
RISCVSystemOperands.td
[RISCV] Initially support the K-extension instructions on the LLVM MC layer
2022-01-24 14:45:35 +08:00
RISCVTargetMachine.cpp
…
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
[RISCV] Add initial support for getRegUsageForType and getNumberOfRegisters
2022-01-17 15:27:54 +08:00
RISCVTargetTransformInfo.h
[RISCV] Add initial support for getRegUsageForType and getNumberOfRegisters
2022-01-17 15:27:54 +08:00