588f121ada
Where the instruction mnemonic contains a dot, we name the corresponding instruction in the .td file using a _ in the place of the dot. e.g. LR_W rather than LRW. This commit updates RISCVInstrInfoZb.td to follow that convention.
279 lines
8.1 KiB
C++
279 lines
8.1 KiB
C++
//===-------------- RISCVSExtWRemoval.cpp - MI sext.w Removal -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===---------------------------------------------------------------------===//
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//
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// This pass removes unneeded sext.w instructions at the MI level.
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//
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//===---------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVSubtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-sextw-removal"
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STATISTIC(NumRemovedSExtW, "Number of removed sign-extensions");
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static cl::opt<bool> DisableSExtWRemoval("riscv-disable-sextw-removal",
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cl::desc("Disable removal of sext.w"),
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cl::init(false), cl::Hidden);
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namespace {
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class RISCVSExtWRemoval : public MachineFunctionPass {
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public:
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static char ID;
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RISCVSExtWRemoval() : MachineFunctionPass(ID) {
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initializeRISCVSExtWRemovalPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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StringRef getPassName() const override { return "RISCV sext.w Removal"; }
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};
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} // end anonymous namespace
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char RISCVSExtWRemoval::ID = 0;
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INITIALIZE_PASS(RISCVSExtWRemoval, DEBUG_TYPE, "RISCV sext.w Removal", false,
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false)
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FunctionPass *llvm::createRISCVSExtWRemovalPass() {
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return new RISCVSExtWRemoval();
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}
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// This function returns true if the machine instruction always outputs a value
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// where bits 63:32 match bit 31.
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// TODO: Allocate a bit in TSFlags for the W instructions?
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// TODO: Add other W instructions.
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static bool isSignExtendingOpW(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case RISCV::LUI:
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case RISCV::LW:
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case RISCV::ADDW:
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case RISCV::ADDIW:
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case RISCV::SUBW:
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case RISCV::MULW:
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case RISCV::SLLW:
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case RISCV::SLLIW:
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case RISCV::SRAW:
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case RISCV::SRAIW:
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case RISCV::SRLW:
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case RISCV::SRLIW:
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case RISCV::DIVW:
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case RISCV::DIVUW:
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case RISCV::REMW:
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case RISCV::REMUW:
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case RISCV::ROLW:
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case RISCV::RORW:
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case RISCV::RORIW:
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case RISCV::CLZW:
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case RISCV::CTZW:
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case RISCV::CPOPW:
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case RISCV::FCVT_W_H:
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case RISCV::FCVT_WU_H:
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case RISCV::FCVT_W_S:
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case RISCV::FCVT_WU_S:
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case RISCV::FCVT_W_D:
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case RISCV::FCVT_WU_D:
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// The following aren't W instructions, but are either sign extended from a
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// smaller size or put zeros in bits 63:31.
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case RISCV::LBU:
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case RISCV::LHU:
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case RISCV::LB:
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case RISCV::LH:
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case RISCV::SLT:
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case RISCV::SLTI:
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case RISCV::SLTU:
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case RISCV::SLTIU:
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case RISCV::SEXT_B:
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case RISCV::SEXT_H:
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case RISCV::ZEXT_H_RV64:
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return true;
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// shifting right sufficiently makes the value 32-bit sign-extended
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case RISCV::SRAI:
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return MI.getOperand(2).getImm() >= 32;
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case RISCV::SRLI:
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return MI.getOperand(2).getImm() > 32;
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// The LI pattern ADDI rd, X0, imm is sign extended.
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case RISCV::ADDI:
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return MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0;
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// An ANDI with an 11 bit immediate will zero bits 63:11.
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case RISCV::ANDI:
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return isUInt<11>(MI.getOperand(2).getImm());
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// An ORI with an >11 bit immediate (negative 12-bit) will set bits 63:11.
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case RISCV::ORI:
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return !isUInt<11>(MI.getOperand(2).getImm());
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// Copying from X0 produces zero.
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case RISCV::COPY:
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return MI.getOperand(1).getReg() == RISCV::X0;
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}
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return false;
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}
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static bool isSignExtendedW(const MachineInstr &OrigMI,
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MachineRegisterInfo &MRI) {
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SmallPtrSet<const MachineInstr *, 4> Visited;
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SmallVector<const MachineInstr *, 4> Worklist;
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Worklist.push_back(&OrigMI);
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while (!Worklist.empty()) {
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const MachineInstr *MI = Worklist.pop_back_val();
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// If we already visited this instruction, we don't need to check it again.
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if (!Visited.insert(MI).second)
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continue;
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// If this is a sign extending operation we don't need to look any further.
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if (isSignExtendingOpW(*MI))
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continue;
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// Is this an instruction that propagates sign extend.
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switch (MI->getOpcode()) {
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default:
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// Unknown opcode, give up.
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return false;
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case RISCV::COPY: {
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Register SrcReg = MI->getOperand(1).getReg();
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// TODO: Handle arguments and returns from calls?
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// If this is a copy from another register, check its source instruction.
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if (!SrcReg.isVirtual())
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return false;
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const MachineInstr *SrcMI = MRI.getVRegDef(SrcReg);
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if (!SrcMI)
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return false;
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// Add SrcMI to the worklist.
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Worklist.push_back(SrcMI);
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break;
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}
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case RISCV::REM:
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case RISCV::ANDI:
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case RISCV::ORI:
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case RISCV::XORI: {
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// |Remainder| is always <= |Dividend|. If D is 32-bit, then so is R.
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// DIV doesn't work because of the edge case 0xf..f 8000 0000 / (long)-1
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// Logical operations use a sign extended 12-bit immediate. We just need
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// to check if the other operand is sign extended.
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Register SrcReg = MI->getOperand(1).getReg();
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if (!SrcReg.isVirtual())
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return false;
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const MachineInstr *SrcMI = MRI.getVRegDef(SrcReg);
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if (!SrcMI)
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return false;
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// Add SrcMI to the worklist.
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Worklist.push_back(SrcMI);
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break;
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}
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case RISCV::REMU:
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case RISCV::AND:
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case RISCV::OR:
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case RISCV::XOR:
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case RISCV::ANDN:
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case RISCV::ORN:
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case RISCV::XNOR:
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case RISCV::MAX:
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case RISCV::MAXU:
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case RISCV::MIN:
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case RISCV::MINU:
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case RISCV::PHI: {
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// If all incoming values are sign-extended, the output of AND, OR, XOR,
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// MIN, MAX, or PHI is also sign-extended.
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// The input registers for PHI are operand 1, 3, ...
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// The input registers for others are operand 1 and 2.
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unsigned E = 3, D = 1;
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if (MI->getOpcode() == RISCV::PHI) {
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E = MI->getNumOperands();
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D = 2;
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}
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for (unsigned I = 1; I != E; I += D) {
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if (!MI->getOperand(I).isReg())
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return false;
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Register SrcReg = MI->getOperand(I).getReg();
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if (!SrcReg.isVirtual())
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return false;
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const MachineInstr *SrcMI = MRI.getVRegDef(SrcReg);
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if (!SrcMI)
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return false;
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// Add SrcMI to the worklist.
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Worklist.push_back(SrcMI);
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}
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break;
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}
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}
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}
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// If we get here, then every node we visited produces a sign extended value
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// or propagated sign extended values. So the result must be sign extended.
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return true;
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}
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bool RISCVSExtWRemoval::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()) || DisableSExtWRemoval)
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return false;
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
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if (!ST.is64Bit())
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return false;
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bool MadeChange = false;
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for (MachineBasicBlock &MBB : MF) {
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for (auto I = MBB.begin(), IE = MBB.end(); I != IE;) {
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MachineInstr *MI = &*I++;
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// We're looking for the sext.w pattern ADDIW rd, rs1, 0.
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if (MI->getOpcode() != RISCV::ADDIW || !MI->getOperand(2).isImm() ||
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MI->getOperand(2).getImm() != 0 || !MI->getOperand(1).isReg())
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continue;
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// Input should be a virtual register.
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Register SrcReg = MI->getOperand(1).getReg();
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if (!SrcReg.isVirtual())
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continue;
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const MachineInstr &SrcMI = *MRI.getVRegDef(SrcReg);
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if (!isSignExtendedW(SrcMI, MRI))
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continue;
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Register DstReg = MI->getOperand(0).getReg();
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if (!MRI.constrainRegClass(SrcReg, MRI.getRegClass(DstReg)))
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continue;
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LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
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MRI.replaceRegWith(DstReg, SrcReg);
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MRI.clearKillFlags(SrcReg);
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MI->eraseFromParent();
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++NumRemovedSExtW;
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MadeChange = true;
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}
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}
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return MadeChange;
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}
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