a2dc4e02e7
This patch enables the multi-group xnack replay mode by configuring the hardware MODE register at kernel entry. This aligns the hardware behavior with the compiler's existing multi-group s_wait_xcnt insertion logic.
60 lines
2.3 KiB
LLVM
60 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 %s -o - | FileCheck -check-prefixes=GCN %s
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; xUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 %s -o - | FileCheck -check-prefix=GCN %s
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; FIXME: GlobalISel does not work with bf16
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declare bfloat @llvm.sin.bf16(bfloat) #0
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define amdgpu_kernel void @sin_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
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; GCN-LABEL: sin_bf16:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
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; GCN-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
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; GCN-NEXT: s_mov_b32 s3, 0x3e230000
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: s_wait_kmcnt 0x0
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
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; GCN-NEXT: v_fma_mixlo_bf16 v0, s2, s3, 0 op_sel_hi:[1,0,0]
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; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GCN-NEXT: v_sin_bf16_e32 v0, v0
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; GCN-NEXT: global_store_b16 v1, v0, s[0:1]
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; GCN-NEXT: s_endpgm
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%sin = call bfloat @llvm.sin.bf16(bfloat %src) #0
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store bfloat %sin, ptr addrspace(1) %out, align 2
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ret void
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}
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define amdgpu_kernel void @sin_bf16_constant_4(ptr addrspace(1) %out) #1 {
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; GCN-LABEL: sin_bf16_constant_4:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
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; GCN-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
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; GCN-NEXT: v_sin_bf16_e32 v0, 0x3f23
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: s_wait_kmcnt 0x0
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; GCN-NEXT: global_store_b16 v1, v0, s[0:1]
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; GCN-NEXT: s_endpgm
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%sin = call bfloat @llvm.sin.bf16(bfloat 4.0) #0
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store bfloat %sin, ptr addrspace(1) %out, align 2
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ret void
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}
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define amdgpu_kernel void @sin_bf16_constant_100(ptr addrspace(1) %out) #1 {
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; GCN-LABEL: sin_bf16_constant_100:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
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; GCN-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
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; GCN-NEXT: v_sin_bf16_e32 v0, 0x417f
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: s_wait_kmcnt 0x0
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; GCN-NEXT: global_store_b16 v1, v0, s[0:1]
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; GCN-NEXT: s_endpgm
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%sin = call bfloat @llvm.sin.bf16(bfloat 100.0) #0
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store bfloat %sin, ptr addrspace(1) %out, align 2
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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