Eugene Zhulenev 68a7c001ad [mlir] Improve async parallel for tests + fix typos ...

Do load and store to verify that we process each element of the iteration space once.

Reviewed By: cota

Differential Revision: https://reviews.llvm.org/D115152

2021-12-06 13:27:54 -08:00

..

Async/CPU

[mlir] Improve async parallel for tests + fix typos

2021-12-06 13:27:54 -08:00

Linalg/CPU

[mlir][linalg] Disable tensor-matmul test under asan

2021-12-01 16:25:31 +01:00

LLVMIR/CPU

[mlir][Vector] Add a vblendps-based impl for transpose8x8 (both intrin and inline_asm)

2021-11-23 07:31:22 +00:00

SparseTensor

[mlir][sparse] Adding a stress test

2021-12-03 14:59:39 -08:00

Standard/CPU

[mlir] Move min/max ops from Std to Arith.

2021-11-15 13:19:17 +01:00

Vector/CPU

[mlir][Vector] Support 0-D vectors in ConstantMaskOp

2021-12-06 08:03:04 +00:00