4beea6b195
There are matching store opcodes (stfd, stxsiwx) for the load opcodes that make 32-bit and 64-bit vector operations cheap with VSX, so stores should also be cheap.
65 lines
1.8 KiB
LLVM
65 lines
1.8 KiB
LLVM
; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 -disable-ppc-unaligned | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define i32 @stores(i32 %arg) {
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; CHECK: cost of 1 {{.*}} store
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store i8 undef, ptr undef, align 4
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; CHECK: cost of 1 {{.*}} store
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store i16 undef, ptr undef, align 4
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; CHECK: cost of 1 {{.*}} store
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store i32 undef, ptr undef, align 4
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; CHECK: cost of 2 {{.*}} store
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store i64 undef, ptr undef, align 4
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; CHECK: cost of 4 {{.*}} store
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store i128 undef, ptr undef, align 4
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ret i32 undef
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}
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define i32 @loads(i32 %arg) {
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; CHECK: cost of 1 {{.*}} load
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load i8, ptr undef, align 4
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; CHECK: cost of 1 {{.*}} load
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load i16, ptr undef, align 4
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; CHECK: cost of 1 {{.*}} load
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load i32, ptr undef, align 4
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; CHECK: cost of 2 {{.*}} load
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load i64, ptr undef, align 4
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; CHECK: cost of 4 {{.*}} load
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load i128, ptr undef, align 4
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; FIXME: There actually are sub-vector Altivec loads, and so we could handle
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; this with a small expense, but we don't currently.
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; CHECK: cost of 42 {{.*}} load
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load <4 x i16>, ptr undef, align 2
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; CHECK: cost of 2 {{.*}} load
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load <4 x i32>, ptr undef, align 4
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; CHECK: cost of 46 {{.*}} load
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load <3 x float>, ptr undef, align 1
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ret i32 undef
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}
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define i32 @partialvector32(i32 %arg) #0 {
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; CHECK: cost of 1 {{.*}} store
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store <4 x i8> undef, ptr undef, align 16
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ret i32 undef
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}
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define i32 @partialvector64(i32 %arg) #1 {
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; CHECK: cost of 1 {{.*}} store
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store <4 x i16> undef, ptr undef, align 16
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ret i32 undef
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}
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attributes #0 = { "target-features"="+power8-vector,+vsx" }
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attributes #1 = { "target-features"="+vsx" }
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