40d952b874
Replacing a free extension with 2 or more extensions unnecessarily increases the number of IR instructions without providing any benefits. It also unnecessarily causes operations to be performed on wider types than necessary. In some cases, the extra extensions also pessimize codegen (see bfis-in-loop.ll). The changes in arm64-codegen-prepare-extload.ll also show that we avoid promotions that should only be performed in stress mode. PR: https://github.com/llvm/llvm-project/pull/77094
146 lines
5.0 KiB
LLVM
146 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: opt -mtriple=aarch64-linux-gnu -passes=typepromotion < %s | llc -mtriple=aarch64-linux-gnu -o - | FileCheck %s
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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%struct.bar = type { %struct.foo }
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%struct.foo = type { ptr }
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%struct.wobble = type { ptr }
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%struct.zot = type <{ %struct.wobble, ptr, ptr, i8, [7 x i8] }>
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@global = external global %struct.bar, align 8
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define i64 @bfis_in_loop_zero() {
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; CHECK-LABEL: bfis_in_loop_zero:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: adrp x8, :got:global
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: mov w9, wzr
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; CHECK-NEXT: ldr x8, [x8, :got_lo12:global]
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; CHECK-NEXT: ldr x8, [x8]
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; CHECK-NEXT: .LBB0_1: // %midblock
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldrh w10, [x8, #72]
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; CHECK-NEXT: ldr x13, [x8, #8]
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; CHECK-NEXT: lsr w11, w10, #8
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; CHECK-NEXT: cmp w10, #0
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; CHECK-NEXT: ldr x8, [x13, #16]
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; CHECK-NEXT: cset w12, ne
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; CHECK-NEXT: csel w9, w9, w11, eq
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; CHECK-NEXT: and x11, x0, #0xffffffff00000000
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; CHECK-NEXT: bfi w10, w9, #8, #24
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; CHECK-NEXT: orr x11, x11, x12, lsl #16
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; CHECK-NEXT: orr x0, x11, x10
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; CHECK-NEXT: cbnz x13, .LBB0_1
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; CHECK-NEXT: // %bb.2: // %exit
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; CHECK-NEXT: ret
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entry:
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%var = load ptr, ptr @global, align 8
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br label %preheader
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preheader:
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br label %header
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header: ; preds = %bb63, %bb
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%var4 = phi i64 [ %var30, %latch ], [ 0, %preheader ]
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%var5 = phi ptr [ %var38, %latch ], [ %var, %preheader ]
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%var6 = phi i8 [ %var21, %latch ], [ 0, %preheader ]
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br label %midblock
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midblock: ; preds = %bb9
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%var15 = getelementptr inbounds %struct.wobble, ptr %var5, i64 9
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%var17 = load i16, ptr %var15, align 8
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%var18 = icmp eq i16 %var17, 0
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%var19 = lshr i16 %var17, 8
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%var20 = trunc i16 %var19 to i8
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%var21 = select i1 %var18, i8 %var6, i8 %var20
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%var22 = zext i8 %var21 to i16
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%var23 = shl nuw i16 %var22, 8
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%var24 = and i16 %var17, 255
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%var25 = or i16 %var23, %var24
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%var26 = select i1 %var18, i64 0, i64 65536
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%var27 = zext i16 %var25 to i64
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%var28 = and i64 %var4, -4294967296
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%var29 = or i64 %var26, %var28
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%var30 = or i64 %var29, %var27
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br label %latch
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latch: ; preds = %bb14, %bb9
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%var34 = getelementptr inbounds %struct.wobble, ptr %var5, i64 1, i32 0
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%var35 = load ptr, ptr %var34, align 8
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%var36 = icmp eq ptr %var35, null
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%var37 = getelementptr inbounds %struct.zot, ptr %var35, i64 0, i32 2
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%var38 = load ptr, ptr %var37, align 8
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br i1 %var36, label %exit, label %header
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exit:
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ret i64 %var30
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}
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define i64 @bfis_in_loop_undef() {
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; CHECK-LABEL: bfis_in_loop_undef:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: adrp x9, :got:global
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; CHECK-NEXT: mov w8, wzr
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; CHECK-NEXT: // implicit-def: $x0
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; CHECK-NEXT: ldr x9, [x9, :got_lo12:global]
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; CHECK-NEXT: ldr x9, [x9]
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; CHECK-NEXT: .LBB1_1: // %midblock
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldrh w10, [x9, #72]
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; CHECK-NEXT: ldr x13, [x9, #8]
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; CHECK-NEXT: lsr w11, w10, #8
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; CHECK-NEXT: cmp w10, #0
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; CHECK-NEXT: ldr x9, [x13, #16]
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; CHECK-NEXT: cset w12, ne
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; CHECK-NEXT: csel w8, w8, w11, eq
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; CHECK-NEXT: and x11, x0, #0xffffffff00000000
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; CHECK-NEXT: bfi w10, w8, #8, #24
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; CHECK-NEXT: orr x11, x11, x12, lsl #16
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; CHECK-NEXT: orr x0, x11, x10
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; CHECK-NEXT: cbnz x13, .LBB1_1
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; CHECK-NEXT: // %bb.2: // %exit
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; CHECK-NEXT: ret
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entry:
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%var = load ptr, ptr @global, align 8
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br label %preheader
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preheader:
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br label %header
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header: ; preds = %bb63, %bb
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%var4 = phi i64 [ %var30, %latch ], [ undef, %preheader ]
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%var5 = phi ptr [ %var38, %latch ], [ %var, %preheader ]
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%var6 = phi i8 [ %var21, %latch ], [ undef, %preheader ]
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br label %midblock
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midblock: ; preds = %bb9
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%var15 = getelementptr inbounds %struct.wobble, ptr %var5, i64 9
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%var17 = load i16, ptr %var15, align 8
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%var18 = icmp eq i16 %var17, 0
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%var19 = lshr i16 %var17, 8
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%var20 = trunc i16 %var19 to i8
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%var21 = select i1 %var18, i8 %var6, i8 %var20
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%var22 = zext i8 %var21 to i16
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%var23 = shl nuw i16 %var22, 8
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%var24 = and i16 %var17, 255
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%var25 = or i16 %var23, %var24
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%var26 = select i1 %var18, i64 0, i64 65536
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%var27 = zext i16 %var25 to i64
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%var28 = and i64 %var4, -4294967296
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%var29 = or i64 %var26, %var28
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%var30 = or i64 %var29, %var27
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br label %latch
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latch: ; preds = %bb14, %bb9
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%var34 = getelementptr inbounds %struct.wobble, ptr %var5, i64 1, i32 0
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%var35 = load ptr, ptr %var34, align 8
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%var36 = icmp eq ptr %var35, null
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%var37 = getelementptr inbounds %struct.zot, ptr %var35, i64 0, i32 2
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%var38 = load ptr, ptr %var37, align 8
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br i1 %var36, label %exit, label %header
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exit:
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ret i64 %var30
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}
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