16e05919d9
The problematic case for unsigned comparisons occurs only when the second argument is zero. The problematic case for signed comparisons occurs only when the second argument is the signed minimum value. We can use KnownBits to know when we don't have to worry about this. Source: https://devblogs.microsoft.com/oldnewthing/20210607-00/?p=105288
504 lines
14 KiB
LLVM
504 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,SDISEL
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; RUN: llc < %s -mtriple=aarch64-- -global-isel | FileCheck %s --check-prefixes=CHECK,GISEL
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; Ensure chains of comparisons produce chains of `ccmp`
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; (x0 < x1) && (x2 > x3)
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define i32 @cmp_and2(i32 %0, i32 %1, i32 %2, i32 %3) {
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; SDISEL-LABEL: cmp_and2:
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; SDISEL: // %bb.0:
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; SDISEL-NEXT: cmp w0, w1
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; SDISEL-NEXT: ccmp w2, w3, #0, lo
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; SDISEL-NEXT: cset w0, hi
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; SDISEL-NEXT: ret
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;
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; GISEL-LABEL: cmp_and2:
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; GISEL: // %bb.0:
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; GISEL-NEXT: cmp w0, w1
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; GISEL-NEXT: cset w8, lo
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; GISEL-NEXT: cmp w2, w3
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; GISEL-NEXT: cset w9, hi
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; GISEL-NEXT: and w0, w8, w9
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; GISEL-NEXT: ret
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%5 = icmp ult i32 %0, %1
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%6 = icmp ugt i32 %2, %3
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%7 = select i1 %5, i1 %6, i1 false
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%8 = zext i1 %7 to i32
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ret i32 %8
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}
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; (x0 < x1) && (x2 > x3) && (x4 != x5)
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define i32 @cmp_and3(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5) {
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; SDISEL-LABEL: cmp_and3:
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; SDISEL: // %bb.0:
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; SDISEL-NEXT: cmp w0, w1
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; SDISEL-NEXT: ccmp w2, w3, #0, lo
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; SDISEL-NEXT: ccmp w4, w5, #4, hi
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; SDISEL-NEXT: cset w0, ne
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; SDISEL-NEXT: ret
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;
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; GISEL-LABEL: cmp_and3:
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; GISEL: // %bb.0:
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; GISEL-NEXT: cmp w0, w1
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; GISEL-NEXT: cset w8, lo
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; GISEL-NEXT: cmp w2, w3
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; GISEL-NEXT: cset w9, hi
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; GISEL-NEXT: cmp w4, w5
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; GISEL-NEXT: and w8, w8, w9
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; GISEL-NEXT: cset w9, ne
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; GISEL-NEXT: and w0, w8, w9
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; GISEL-NEXT: ret
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%7 = icmp ult i32 %0, %1
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%8 = icmp ugt i32 %2, %3
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%9 = select i1 %7, i1 %8, i1 false
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%10 = icmp ne i32 %4, %5
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%11 = select i1 %9, i1 %10, i1 false
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%12 = zext i1 %11 to i32
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ret i32 %12
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}
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; (x0 < x1) && (x2 > x3) && (x4 != x5) && (x6 == x7)
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define i32 @cmp_and4(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7) {
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; SDISEL-LABEL: cmp_and4:
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; SDISEL: // %bb.0:
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; SDISEL-NEXT: cmp w2, w3
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; SDISEL-NEXT: ccmp w0, w1, #2, hi
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; SDISEL-NEXT: ccmp w4, w5, #4, lo
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; SDISEL-NEXT: ccmp w6, w7, #0, ne
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; SDISEL-NEXT: cset w0, eq
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; SDISEL-NEXT: ret
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;
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; GISEL-LABEL: cmp_and4:
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; GISEL: // %bb.0:
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; GISEL-NEXT: cmp w2, w3
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; GISEL-NEXT: cset w8, hi
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; GISEL-NEXT: cmp w0, w1
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; GISEL-NEXT: cset w9, lo
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; GISEL-NEXT: cmp w4, w5
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; GISEL-NEXT: cset w10, ne
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; GISEL-NEXT: cmp w6, w7
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; GISEL-NEXT: and w8, w8, w9
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; GISEL-NEXT: cset w11, eq
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; GISEL-NEXT: and w9, w10, w11
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; GISEL-NEXT: and w0, w8, w9
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; GISEL-NEXT: ret
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%9 = icmp ugt i32 %2, %3
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%10 = icmp ult i32 %0, %1
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%11 = select i1 %9, i1 %10, i1 false
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%12 = icmp ne i32 %4, %5
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%13 = select i1 %11, i1 %12, i1 false
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%14 = icmp eq i32 %6, %7
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%15 = select i1 %13, i1 %14, i1 false
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%16 = zext i1 %15 to i32
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ret i32 %16
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}
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; (x0 < x1) || (x2 > x3)
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define i32 @cmp_or2(i32 %0, i32 %1, i32 %2, i32 %3) {
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; SDISEL-LABEL: cmp_or2:
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; SDISEL: // %bb.0:
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; SDISEL-NEXT: cmp w0, w1
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; SDISEL-NEXT: ccmp w2, w3, #0, hs
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; SDISEL-NEXT: cset w0, ne
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; SDISEL-NEXT: ret
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;
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; GISEL-LABEL: cmp_or2:
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; GISEL: // %bb.0:
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; GISEL-NEXT: cmp w0, w1
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; GISEL-NEXT: cset w8, lo
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; GISEL-NEXT: cmp w2, w3
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; GISEL-NEXT: cset w9, ne
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; GISEL-NEXT: orr w8, w8, w9
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; GISEL-NEXT: and w0, w8, #0x1
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; GISEL-NEXT: ret
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%5 = icmp ult i32 %0, %1
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%6 = icmp ne i32 %2, %3
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%7 = select i1 %5, i1 true, i1 %6
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%8 = zext i1 %7 to i32
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ret i32 %8
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}
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; (x0 < x1) || (x2 > x3) || (x4 != x5)
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define i32 @cmp_or3(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5) {
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; SDISEL-LABEL: cmp_or3:
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; SDISEL: // %bb.0:
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; SDISEL-NEXT: cmp w0, w1
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; SDISEL-NEXT: ccmp w2, w3, #2, hs
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; SDISEL-NEXT: ccmp w4, w5, #0, ls
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; SDISEL-NEXT: cset w0, ne
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; SDISEL-NEXT: ret
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;
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; GISEL-LABEL: cmp_or3:
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; GISEL: // %bb.0:
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; GISEL-NEXT: cmp w0, w1
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; GISEL-NEXT: cset w8, lo
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; GISEL-NEXT: cmp w2, w3
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; GISEL-NEXT: cset w9, hi
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; GISEL-NEXT: cmp w4, w5
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; GISEL-NEXT: orr w8, w8, w9
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; GISEL-NEXT: cset w9, ne
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; GISEL-NEXT: orr w8, w8, w9
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; GISEL-NEXT: and w0, w8, #0x1
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; GISEL-NEXT: ret
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%7 = icmp ult i32 %0, %1
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%8 = icmp ugt i32 %2, %3
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%9 = select i1 %7, i1 true, i1 %8
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%10 = icmp ne i32 %4, %5
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%11 = select i1 %9, i1 true, i1 %10
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%12 = zext i1 %11 to i32
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ret i32 %12
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}
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; (x0 < x1) || (x2 > x3) || (x4 != x5) || (x6 == x7)
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define i32 @cmp_or4(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7) {
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; SDISEL-LABEL: cmp_or4:
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; SDISEL: // %bb.0:
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; SDISEL-NEXT: cmp w0, w1
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; SDISEL-NEXT: ccmp w2, w3, #2, hs
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; SDISEL-NEXT: ccmp w4, w5, #0, ls
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; SDISEL-NEXT: ccmp w6, w7, #4, eq
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; SDISEL-NEXT: cset w0, eq
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; SDISEL-NEXT: ret
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;
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; GISEL-LABEL: cmp_or4:
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; GISEL: // %bb.0:
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; GISEL-NEXT: cmp w0, w1
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; GISEL-NEXT: cset w8, lo
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; GISEL-NEXT: cmp w2, w3
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; GISEL-NEXT: cset w9, hi
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; GISEL-NEXT: cmp w4, w5
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; GISEL-NEXT: cset w10, ne
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; GISEL-NEXT: cmp w6, w7
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; GISEL-NEXT: orr w8, w8, w9
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; GISEL-NEXT: cset w11, eq
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; GISEL-NEXT: orr w9, w10, w11
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; GISEL-NEXT: orr w8, w8, w9
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; GISEL-NEXT: and w0, w8, #0x1
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; GISEL-NEXT: ret
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%9 = icmp ult i32 %0, %1
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%10 = icmp ugt i32 %2, %3
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%11 = select i1 %9, i1 true, i1 %10
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%12 = icmp ne i32 %4, %5
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%13 = select i1 %11, i1 true, i1 %12
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%14 = icmp eq i32 %6, %7
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%15 = select i1 %13, i1 true, i1 %14
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%16 = zext i1 %15 to i32
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ret i32 %16
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}
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; (x0 != 0) || (x1 != 0)
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define i32 @true_or2(i32 %0, i32 %1) {
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; SDISEL-LABEL: true_or2:
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; SDISEL: // %bb.0:
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; SDISEL-NEXT: orr w8, w0, w1
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; SDISEL-NEXT: cmp w8, #0
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; SDISEL-NEXT: cset w0, ne
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; SDISEL-NEXT: ret
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;
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; GISEL-LABEL: true_or2:
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; GISEL: // %bb.0:
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; GISEL-NEXT: cmp w0, #0
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; GISEL-NEXT: cset w8, ne
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; GISEL-NEXT: cmp w1, #0
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; GISEL-NEXT: cset w9, ne
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; GISEL-NEXT: orr w8, w8, w9
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; GISEL-NEXT: and w0, w8, #0x1
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; GISEL-NEXT: ret
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%3 = icmp ne i32 %0, 0
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%4 = icmp ne i32 %1, 0
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%5 = select i1 %3, i1 true, i1 %4
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%6 = zext i1 %5 to i32
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ret i32 %6
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}
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; (x0 != 0) || (x1 != 0) || (x2 != 0)
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define i32 @true_or3(i32 %0, i32 %1, i32 %2) {
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; SDISEL-LABEL: true_or3:
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; SDISEL: // %bb.0:
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; SDISEL-NEXT: orr w8, w0, w1
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; SDISEL-NEXT: orr w8, w8, w2
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; SDISEL-NEXT: cmp w8, #0
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; SDISEL-NEXT: cset w0, ne
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; SDISEL-NEXT: ret
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;
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; GISEL-LABEL: true_or3:
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; GISEL: // %bb.0:
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; GISEL-NEXT: cmp w0, #0
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; GISEL-NEXT: cset w8, ne
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; GISEL-NEXT: cmp w1, #0
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; GISEL-NEXT: cset w9, ne
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; GISEL-NEXT: cmp w2, #0
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; GISEL-NEXT: orr w8, w8, w9
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; GISEL-NEXT: cset w9, ne
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; GISEL-NEXT: orr w8, w8, w9
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; GISEL-NEXT: and w0, w8, #0x1
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; GISEL-NEXT: ret
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%4 = icmp ne i32 %0, 0
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%5 = icmp ne i32 %1, 0
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%6 = select i1 %4, i1 true, i1 %5
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%7 = icmp ne i32 %2, 0
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%8 = select i1 %6, i1 true, i1 %7
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%9 = zext i1 %8 to i32
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ret i32 %9
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}
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; (b > -3 && a < c)
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define i32 @neg_range_int(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: neg_range_int:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, w2
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; CHECK-NEXT: ccmn w1, #3, #4, lt
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; CHECK-NEXT: csel w0, w1, w0, gt
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; CHECK-NEXT: ret
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%cmp = icmp sgt i32 %b, -3
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%cmp1 = icmp slt i32 %a, %c
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%or.cond = and i1 %cmp, %cmp1
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%retval.0 = select i1 %or.cond, i32 %b, i32 %a
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ret i32 %retval.0
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}
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; (b > -(d | 1) && a < c)
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define i32 @neg_range_int_comp(i32 %a, i32 %b, i32 %c, i32 %d) {
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; SDISEL-LABEL: neg_range_int_comp:
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; SDISEL: // %bb.0:
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; SDISEL-NEXT: orr w8, w3, #0x1
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; SDISEL-NEXT: cmp w0, w2
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; SDISEL-NEXT: ccmn w1, w8, #4, lt
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; SDISEL-NEXT: csel w0, w1, w0, gt
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; SDISEL-NEXT: ret
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;
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; GISEL-LABEL: neg_range_int_comp:
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; GISEL: // %bb.0:
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; GISEL-NEXT: orr w8, w3, #0x1
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; GISEL-NEXT: cmp w0, w2
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; GISEL-NEXT: neg w8, w8
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; GISEL-NEXT: ccmp w1, w8, #4, lt
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; GISEL-NEXT: csel w0, w1, w0, gt
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; GISEL-NEXT: ret
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%dor = or i32 %d, 1
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%negd = sub i32 0, %dor
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%cmp = icmp sgt i32 %b, %negd
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%cmp1 = icmp slt i32 %a, %c
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%or.cond = and i1 %cmp, %cmp1
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%retval.0 = select i1 %or.cond, i32 %b, i32 %a
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ret i32 %retval.0
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}
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; (b >u -(d | 1) && a < c)
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define i32 @neg_range_int_comp_u(i32 %a, i32 %b, i32 %c, i32 %d) {
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; SDISEL-LABEL: neg_range_int_comp_u:
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; SDISEL: // %bb.0:
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; SDISEL-NEXT: orr w8, w3, #0x1
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; SDISEL-NEXT: cmp w0, w2
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; SDISEL-NEXT: ccmn w1, w8, #0, lt
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; SDISEL-NEXT: csel w0, w1, w0, hi
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; SDISEL-NEXT: ret
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;
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; GISEL-LABEL: neg_range_int_comp_u:
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; GISEL: // %bb.0:
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; GISEL-NEXT: orr w8, w3, #0x1
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; GISEL-NEXT: cmp w0, w2
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; GISEL-NEXT: neg w8, w8
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; GISEL-NEXT: ccmp w1, w8, #0, lt
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; GISEL-NEXT: csel w0, w1, w0, hi
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; GISEL-NEXT: ret
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%dor = or i32 %d, 1
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%negd = sub i32 0, %dor
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%cmp = icmp ugt i32 %b, %negd
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%cmp1 = icmp slt i32 %a, %c
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%or.cond = and i1 %cmp, %cmp1
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%retval.0 = select i1 %or.cond, i32 %b, i32 %a
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ret i32 %retval.0
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}
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; (b > -(d | 1) && a u < c)
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define i32 @neg_range_int_comp_ua(i32 %a, i32 %b, i32 %c, i32 %d) {
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; SDISEL-LABEL: neg_range_int_comp_ua:
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; SDISEL: // %bb.0:
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; SDISEL-NEXT: orr w8, w3, #0x1
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; SDISEL-NEXT: cmp w0, w2
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; SDISEL-NEXT: ccmn w1, w8, #4, lo
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; SDISEL-NEXT: csel w0, w1, w0, gt
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; SDISEL-NEXT: ret
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;
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; GISEL-LABEL: neg_range_int_comp_ua:
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; GISEL: // %bb.0:
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; GISEL-NEXT: orr w8, w3, #0x1
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; GISEL-NEXT: cmp w0, w2
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; GISEL-NEXT: neg w8, w8
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; GISEL-NEXT: ccmp w1, w8, #4, lo
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; GISEL-NEXT: csel w0, w1, w0, gt
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; GISEL-NEXT: ret
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%dor = or i32 %d, 1
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%negd = sub i32 0, %dor
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%cmp = icmp sgt i32 %b, %negd
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%cmp1 = icmp ult i32 %a, %c
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%or.cond = and i1 %cmp, %cmp1
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%retval.0 = select i1 %or.cond, i32 %b, i32 %a
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ret i32 %retval.0
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}
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; (b <= -3 && a > c)
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define i32 @neg_range_int_2(i32 %a, i32 %b, i32 %c) {
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; SDISEL-LABEL: neg_range_int_2:
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; SDISEL: // %bb.0:
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; SDISEL-NEXT: cmp w0, w2
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; SDISEL-NEXT: ccmn w1, #4, #4, gt
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; SDISEL-NEXT: csel w0, w1, w0, gt
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; SDISEL-NEXT: ret
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;
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; GISEL-LABEL: neg_range_int_2:
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; GISEL: // %bb.0:
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; GISEL-NEXT: cmp w0, w2
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; GISEL-NEXT: ccmn w1, #3, #8, gt
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; GISEL-NEXT: csel w0, w1, w0, ge
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; GISEL-NEXT: ret
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%cmp = icmp sge i32 %b, -3
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%cmp1 = icmp sgt i32 %a, %c
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%or.cond = and i1 %cmp, %cmp1
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%retval.0 = select i1 %or.cond, i32 %b, i32 %a
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ret i32 %retval.0
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}
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; (b < -(d | 1) && a >= c)
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define i32 @neg_range_int_comp2(i32 %a, i32 %b, i32 %c, i32 %d) {
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; SDISEL-LABEL: neg_range_int_comp2:
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; SDISEL: // %bb.0:
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; SDISEL-NEXT: orr w8, w3, #0x1
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; SDISEL-NEXT: cmp w0, w2
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; SDISEL-NEXT: ccmn w1, w8, #0, ge
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; SDISEL-NEXT: csel w0, w1, w0, lt
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; SDISEL-NEXT: ret
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;
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; GISEL-LABEL: neg_range_int_comp2:
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; GISEL: // %bb.0:
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; GISEL-NEXT: orr w8, w3, #0x1
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; GISEL-NEXT: cmp w0, w2
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; GISEL-NEXT: neg w8, w8
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|
; GISEL-NEXT: ccmp w1, w8, #0, ge
|
|
; GISEL-NEXT: csel w0, w1, w0, lt
|
|
; GISEL-NEXT: ret
|
|
%dor = or i32 %d, 1
|
|
%negd = sub i32 0, %dor
|
|
%cmp = icmp slt i32 %b, %negd
|
|
%cmp1 = icmp sge i32 %a, %c
|
|
%or.cond = and i1 %cmp, %cmp1
|
|
%retval.0 = select i1 %or.cond, i32 %b, i32 %a
|
|
ret i32 %retval.0
|
|
}
|
|
|
|
; (b <u -(d | 1) && a > c)
|
|
define i32 @neg_range_int_comp_u2(i32 %a, i32 %b, i32 %c, i32 %d) {
|
|
; SDISEL-LABEL: neg_range_int_comp_u2:
|
|
; SDISEL: // %bb.0:
|
|
; SDISEL-NEXT: orr w8, w3, #0x1
|
|
; SDISEL-NEXT: cmp w0, w2
|
|
; SDISEL-NEXT: ccmn w1, w8, #2, gt
|
|
; SDISEL-NEXT: csel w0, w1, w0, lo
|
|
; SDISEL-NEXT: ret
|
|
;
|
|
; GISEL-LABEL: neg_range_int_comp_u2:
|
|
; GISEL: // %bb.0:
|
|
; GISEL-NEXT: orr w8, w3, #0x1
|
|
; GISEL-NEXT: cmp w0, w2
|
|
; GISEL-NEXT: neg w8, w8
|
|
; GISEL-NEXT: ccmp w1, w8, #2, gt
|
|
; GISEL-NEXT: csel w0, w1, w0, lo
|
|
; GISEL-NEXT: ret
|
|
%dor = or i32 %d, 1
|
|
%negd = sub i32 0, %dor
|
|
%cmp = icmp ult i32 %b, %negd
|
|
%cmp1 = icmp sgt i32 %a, %c
|
|
%or.cond = and i1 %cmp, %cmp1
|
|
%retval.0 = select i1 %or.cond, i32 %b, i32 %a
|
|
ret i32 %retval.0
|
|
}
|
|
|
|
; (b > -(d | 1) && a u > c)
|
|
define i32 @neg_range_int_comp_ua2(i32 %a, i32 %b, i32 %c, i32 %d) {
|
|
; SDISEL-LABEL: neg_range_int_comp_ua2:
|
|
; SDISEL: // %bb.0:
|
|
; SDISEL-NEXT: orr w8, w3, #0x1
|
|
; SDISEL-NEXT: cmp w0, w2
|
|
; SDISEL-NEXT: ccmn w1, w8, #4, hi
|
|
; SDISEL-NEXT: csel w0, w1, w0, gt
|
|
; SDISEL-NEXT: ret
|
|
;
|
|
; GISEL-LABEL: neg_range_int_comp_ua2:
|
|
; GISEL: // %bb.0:
|
|
; GISEL-NEXT: orr w8, w3, #0x1
|
|
; GISEL-NEXT: cmp w0, w2
|
|
; GISEL-NEXT: neg w8, w8
|
|
; GISEL-NEXT: ccmp w1, w8, #4, hi
|
|
; GISEL-NEXT: csel w0, w1, w0, gt
|
|
; GISEL-NEXT: ret
|
|
%dor = or i32 %d, 1
|
|
%negd = sub i32 0, %dor
|
|
%cmp = icmp sgt i32 %b, %negd
|
|
%cmp1 = icmp ugt i32 %a, %c
|
|
%or.cond = and i1 %cmp, %cmp1
|
|
%retval.0 = select i1 %or.cond, i32 %b, i32 %a
|
|
ret i32 %retval.0
|
|
}
|
|
|
|
; (b > -(d | 1) && a u == c)
|
|
define i32 @neg_range_int_comp_ua3(i32 %a, i32 %b, i32 %c, i32 %d) {
|
|
; SDISEL-LABEL: neg_range_int_comp_ua3:
|
|
; SDISEL: // %bb.0:
|
|
; SDISEL-NEXT: orr w8, w3, #0x1
|
|
; SDISEL-NEXT: cmp w0, w2
|
|
; SDISEL-NEXT: ccmn w1, w8, #4, eq
|
|
; SDISEL-NEXT: csel w0, w1, w0, gt
|
|
; SDISEL-NEXT: ret
|
|
;
|
|
; GISEL-LABEL: neg_range_int_comp_ua3:
|
|
; GISEL: // %bb.0:
|
|
; GISEL-NEXT: orr w8, w3, #0x1
|
|
; GISEL-NEXT: cmp w0, w2
|
|
; GISEL-NEXT: neg w8, w8
|
|
; GISEL-NEXT: ccmp w1, w8, #4, eq
|
|
; GISEL-NEXT: csel w0, w1, w0, gt
|
|
; GISEL-NEXT: ret
|
|
%dor = or i32 %d, 1
|
|
%negd = sub i32 0, %dor
|
|
%cmp = icmp sgt i32 %b, %negd
|
|
%cmp1 = icmp eq i32 %a, %c
|
|
%or.cond = and i1 %cmp, %cmp1
|
|
%retval.0 = select i1 %or.cond, i32 %b, i32 %a
|
|
ret i32 %retval.0
|
|
}
|
|
|
|
; -(a | 1) > (b | 3) && a < c
|
|
define i32 @neg_range_int_c(i32 %a, i32 %b, i32 %c) {
|
|
; SDISEL-LABEL: neg_range_int_c:
|
|
; SDISEL: // %bb.0: // %entry
|
|
; SDISEL-NEXT: orr w8, w0, #0x1
|
|
; SDISEL-NEXT: orr w9, w1, #0x3
|
|
; SDISEL-NEXT: cmn w9, w8
|
|
; SDISEL-NEXT: ccmp w2, w0, #2, lo
|
|
; SDISEL-NEXT: cset w0, lo
|
|
; SDISEL-NEXT: ret
|
|
;
|
|
; GISEL-LABEL: neg_range_int_c:
|
|
; GISEL: // %bb.0: // %entry
|
|
; GISEL-NEXT: orr w8, w0, #0x1
|
|
; GISEL-NEXT: orr w9, w1, #0x3
|
|
; GISEL-NEXT: neg w8, w8
|
|
; GISEL-NEXT: cmp w9, w8
|
|
; GISEL-NEXT: cset w8, lo
|
|
; GISEL-NEXT: cmp w2, w0
|
|
; GISEL-NEXT: cset w9, lo
|
|
; GISEL-NEXT: and w0, w8, w9
|
|
; GISEL-NEXT: ret
|
|
entry:
|
|
%or = or i32 %a, 1
|
|
%sub = sub i32 0, %or
|
|
%or1 = or i32 %b, 3
|
|
%cmp = icmp ult i32 %or1, %sub
|
|
%cmp2 = icmp ult i32 %c, %a
|
|
%0 = and i1 %cmp, %cmp2
|
|
%land.ext = zext i1 %0 to i32
|
|
ret i32 %land.ext
|
|
}
|