61510b51c3
This reverts commit 9c319d5bb40785c969d2af76535ca62448dfafa7. Some issues were discovered with the bootstrap builds, which seem like they were caused by this commit. I'm reverting to investigate.
196 lines
7.6 KiB
LLVM
196 lines
7.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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define <2 x i32> @and_extract_zext_idx0(<4 x i16> %vec) nounwind {
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; CHECK-SD-LABEL: and_extract_zext_idx0:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
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; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: and_extract_zext_idx0:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: movi d1, #0x00ffff0000ffff
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; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
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; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
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; CHECK-GI-NEXT: ret
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%zext = zext <4 x i16> %vec to <4 x i32>
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%extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 0)
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%and = and <2 x i32> %extract, <i32 65535, i32 65535>
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ret <2 x i32> %and
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}
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define <4 x i16> @and_extract_sext_idx0(<8 x i8> %vec) nounwind {
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; CHECK-SD-LABEL: and_extract_sext_idx0:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
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; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: and_extract_sext_idx0:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff
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; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
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; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
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; CHECK-GI-NEXT: ret
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%sext = sext <8 x i8> %vec to <8 x i16>
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%extract = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %sext, i64 0)
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%and = and <4 x i16> %extract, <i16 255, i16 255, i16 255, i16 255>
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ret <4 x i16> %and
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}
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define <2 x i32> @and_extract_zext_idx2(<4 x i16> %vec) nounwind {
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; CHECK-SD-LABEL: and_extract_zext_idx2:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
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; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: and_extract_zext_idx2:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
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; CHECK-GI-NEXT: movi d1, #0x00ffff0000ffff
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; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
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; CHECK-GI-NEXT: ret
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%zext = zext <4 x i16> %vec to <4 x i32>
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%extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 2)
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%and = and <2 x i32> %extract, <i32 65535, i32 65535>
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ret <2 x i32> %and
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}
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define <4 x i16> @and_extract_sext_idx4(<8 x i8> %vec) nounwind {
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; CHECK-SD-LABEL: and_extract_sext_idx4:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
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; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: and_extract_sext_idx4:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
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; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff
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; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
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; CHECK-GI-NEXT: ret
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%sext = sext <8 x i8> %vec to <8 x i16>
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%extract = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %sext, i64 4)
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%and = and <4 x i16> %extract, <i16 255, i16 255, i16 255, i16 255>
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ret <4 x i16> %and
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}
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define <2 x i32> @sext_extract_zext_idx0(<4 x i16> %vec) nounwind {
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; CHECK-SD-LABEL: sext_extract_zext_idx0:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #0
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; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: sext_extract_zext_idx0:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
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; CHECK-GI-NEXT: shl v0.2s, v0.2s, #16
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; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #16
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; CHECK-GI-NEXT: ret
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%zext = zext <4 x i16> %vec to <4 x i32>
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%extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 0)
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%sext_inreg_step0 = shl <2 x i32> %extract, <i32 16, i32 16>
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%sext_inreg = ashr <2 x i32> %sext_inreg_step0, <i32 16, i32 16>
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ret <2 x i32> %sext_inreg
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}
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; Negative test, combine should not fire if sign extension is for a different width.
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define <2 x i32> @sext_extract_zext_idx0_negtest(<4 x i16> %vec) nounwind {
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; CHECK-LABEL: sext_extract_zext_idx0_negtest:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushll v0.4s, v0.4h, #0
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; CHECK-NEXT: shl v0.2s, v0.2s, #17
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; CHECK-NEXT: sshr v0.2s, v0.2s, #17
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; CHECK-NEXT: ret
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%zext = zext <4 x i16> %vec to <4 x i32>
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%extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 0)
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%sext_inreg_step0 = shl <2 x i32> %extract, <i32 17, i32 17>
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%sext_inreg = ashr <2 x i32> %sext_inreg_step0, <i32 17, i32 17>
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ret <2 x i32> %sext_inreg
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}
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define <4 x i16> @sext_extract_sext_idx0(<8 x i8> %vec) nounwind {
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; CHECK-SD-LABEL: sext_extract_sext_idx0:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0
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; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: sext_extract_sext_idx0:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
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; CHECK-GI-NEXT: shl v0.4h, v0.4h, #8
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; CHECK-GI-NEXT: sshr v0.4h, v0.4h, #8
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; CHECK-GI-NEXT: ret
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%sext = sext <8 x i8> %vec to <8 x i16>
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%extract = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %sext, i64 0)
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%sext_inreg_step0 = shl <4 x i16> %extract, <i16 8, i16 8, i16 8, i16 8>
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%sext_inreg = ashr <4 x i16> %sext_inreg_step0, <i16 8, i16 8, i16 8, i16 8>
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ret <4 x i16> %sext_inreg
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}
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define <2 x i32> @sext_extract_zext_idx2(<4 x i16> %vec) nounwind {
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; CHECK-SD-LABEL: sext_extract_zext_idx2:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #0
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; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: sext_extract_zext_idx2:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
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; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-GI-NEXT: shl v0.2s, v0.2s, #16
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; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #16
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; CHECK-GI-NEXT: ret
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%zext = zext <4 x i16> %vec to <4 x i32>
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%extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 2)
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%sext_inreg_step0 = shl <2 x i32> %extract, <i32 16, i32 16>
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%sext_inreg = ashr <2 x i32> %sext_inreg_step0, <i32 16, i32 16>
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ret <2 x i32> %sext_inreg
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}
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define <4 x i16> @sext_extract_sext_idx4(<8 x i8> %vec) nounwind {
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; CHECK-SD-LABEL: sext_extract_sext_idx4:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0
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; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: sext_extract_sext_idx4:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
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; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-GI-NEXT: shl v0.4h, v0.4h, #8
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; CHECK-GI-NEXT: sshr v0.4h, v0.4h, #8
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; CHECK-GI-NEXT: ret
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%sext = sext <8 x i8> %vec to <8 x i16>
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%extract = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %sext, i64 4)
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%sext_inreg_step0 = shl <4 x i16> %extract, <i16 8, i16 8, i16 8, i16 8>
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%sext_inreg = ashr <4 x i16> %sext_inreg_step0, <i16 8, i16 8, i16 8, i16 8>
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ret <4 x i16> %sext_inreg
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}
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define <8 x i8> @sext_extract_idx(<16 x i8> %vec) nounwind {
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; CHECK-LABEL: sext_extract_idx:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-NEXT: ret
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%extract = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %vec, i64 0)
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ret <8 x i8> %extract
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}
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declare <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32>, i64)
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declare <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16>, i64)
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declare <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8>, i64)
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