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llvm-project/llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
Sander de Smalen 61510b51c3 Revert "[AArch64] Enable subreg liveness tracking by default." 
This reverts commit 9c319d5bb40785c969d2af76535ca62448dfafa7.

Some issues were discovered with the bootstrap builds, which
seem like they were caused by this commit. I'm reverting to investigate.
2024-12-12 17:22:15 +00:00

188 lines
6.8 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -aarch64-min-jump-table-entries=4 -mtriple=arm64-apple-ios < %s | FileCheck %s
; Check there's no assert in spilling from implicit-def operands on an
; IMPLICIT_DEF.
define void @widget(i32 %arg, i32 %arg1, ptr %arg2, ptr %arg3, ptr %arg4, i32 %arg5, i1 %arg6) {
; CHECK-LABEL: widget:
; CHECK: ; %bb.0: ; %bb
; CHECK-NEXT: sub sp, sp, #144
; CHECK-NEXT: stp x28, x27, [sp, #48] ; 16-byte Folded Spill
; CHECK-NEXT: stp x26, x25, [sp, #64] ; 16-byte Folded Spill
; CHECK-NEXT: stp x24, x23, [sp, #80] ; 16-byte Folded Spill
; CHECK-NEXT: stp x22, x21, [sp, #96] ; 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #112] ; 16-byte Folded Spill
; CHECK-NEXT: stp x29, x30, [sp, #128] ; 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 144
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: .cfi_offset w19, -24
; CHECK-NEXT: .cfi_offset w20, -32
; CHECK-NEXT: .cfi_offset w21, -40
; CHECK-NEXT: .cfi_offset w22, -48
; CHECK-NEXT: .cfi_offset w23, -56
; CHECK-NEXT: .cfi_offset w24, -64
; CHECK-NEXT: .cfi_offset w25, -72
; CHECK-NEXT: .cfi_offset w26, -80
; CHECK-NEXT: .cfi_offset w27, -88
; CHECK-NEXT: .cfi_offset w28, -96
; CHECK-NEXT: mov w19, w6
; CHECK-NEXT: mov w20, w5
; CHECK-NEXT: mov x21, x4
; CHECK-NEXT: mov x22, x3
; CHECK-NEXT: mov x23, x2
; CHECK-NEXT: mov w24, w1
; CHECK-NEXT: mov w25, w0
; CHECK-NEXT: mov w26, w1
; CHECK-NEXT: Lloh0:
; CHECK-NEXT: adrp x27, LJTI0_0@PAGE
; CHECK-NEXT: Lloh1:
; CHECK-NEXT: add x27, x27, LJTI0_0@PAGEOFF
; CHECK-NEXT: mov w28, #1 ; =0x1
; CHECK-NEXT: ; implicit-def: $w8
; CHECK-NEXT: str x8, [sp, #40] ; 8-byte Folded Spill
; CHECK-NEXT: b LBB0_2
; CHECK-NEXT: LBB0_1: ; %bb10
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: mov w0, w20
; CHECK-NEXT: mov x1, x22
; CHECK-NEXT: str wzr, [x21]
; CHECK-NEXT: bl _putc
; CHECK-NEXT: mov w0, w25
; CHECK-NEXT: mov x1, xzr
; CHECK-NEXT: bl _putc
; CHECK-NEXT: LBB0_2: ; %bb8
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: cmp w24, #39
; CHECK-NEXT: b.hi LBB0_5
; CHECK-NEXT: ; %bb.3: ; %bb8
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: adr x8, LBB0_1
; CHECK-NEXT: ldrb w9, [x27, x26]
; CHECK-NEXT: add x8, x8, x9, lsl #2
; CHECK-NEXT: br x8
; CHECK-NEXT: LBB0_4: ; %bb9
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: str w28, [x23]
; CHECK-NEXT: b LBB0_2
; CHECK-NEXT: LBB0_5: ; %bb8
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: cmp w24, #64
; CHECK-NEXT: b.ne LBB0_2
; CHECK-NEXT: b LBB0_9
; CHECK-NEXT: LBB0_6: ; %bb13
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: mov w8, #1 ; =0x1
; CHECK-NEXT: str x8, [sp, #40] ; 8-byte Folded Spill
; CHECK-NEXT: tbz w19, #0, LBB0_2
; CHECK-NEXT: ; %bb.7: ; %bb14
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: mov x1, xzr
; CHECK-NEXT: mov w8, #1 ; =0x1
; CHECK-NEXT: stp xzr, xzr, [sp]
; CHECK-NEXT: stp x8, xzr, [sp, #16]
; CHECK-NEXT: bl _fprintf
; CHECK-NEXT: b LBB0_2
; CHECK-NEXT: LBB0_8: ; %bb12
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: b LBB0_8
; CHECK-NEXT: LBB0_9: ; %bb16
; CHECK-NEXT: ldr x8, [sp, #40] ; 8-byte Folded Reload
; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: mov x1, xzr
; CHECK-NEXT: ; kill: def $w8 killed $w8 killed $x8 def $x8
; CHECK-NEXT: str x8, [sp]
; CHECK-NEXT: bl _fprintf
; CHECK-NEXT: brk #0x1
; CHECK-NEXT: .loh AdrpAdd Lloh0, Lloh1
; CHECK-NEXT: .cfi_endproc
; CHECK-NEXT: .section __TEXT,__const
; CHECK-NEXT: LJTI0_0:
; CHECK-NEXT: .byte (LBB0_6-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_8-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_4-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_1-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_2-LBB0_1)>>2
; CHECK-NEXT: .byte (LBB0_1-LBB0_1)>>2
bb:
br label %bb7
bb7: ; preds = %bb14, %bb13, %bb
%phi = phi i32 [ poison, %bb ], [ %mul, %bb14 ], [ %mul, %bb13 ]
br label %bb8
bb8: ; preds = %bb10, %bb9, %bb8, %bb7
switch i32 %arg1, label %bb8 [
i32 10, label %bb9
i32 64, label %bb16
i32 0, label %bb13
i32 39, label %bb10
i32 34, label %bb10
i32 1, label %bb12
]
bb9: ; preds = %bb8
store i32 1, ptr %arg2, align 4
br label %bb8
bb10: ; preds = %bb8, %bb8
store i32 0, ptr %arg4, align 4
%call = tail call i32 @putc(i32 %arg5, ptr %arg3)
%call11 = tail call i32 @putc(i32 %arg, ptr null)
br label %bb8
bb12: ; preds = %bb12, %bb8
br label %bb12
bb13: ; preds = %bb8
%mul = mul i32 1, 1
br i1 %arg6, label %bb14, label %bb7
bb14: ; preds = %bb13
%call15 = tail call i32 (ptr, ptr, ...) @fprintf(ptr null, ptr null, ptr null, i32 0, i32 %mul, ptr null)
br label %bb7
bb16: ; preds = %bb8
%call17 = tail call i32 (ptr, ptr, ...) @fprintf(ptr null, ptr null, i32 %phi)
unreachable
}
declare i32 @fprintf(ptr, ptr, ...)
declare i32 @putc(i32, ptr)
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