b2073fb9b9
When the predicate of a destructive operation is known to be all-true,
for example
fabs z0.s, p0/m, z1.s
then the entire output register is written and we can use a zeroing
(instead of a merging) form of the instruction, for example
fabs z0.s, p0/z, z1.s
thus eliminate the dependency on the input-output destination register
without the need to insert a `movprfx`.
This patch complements (and in the case of
2b3266c170,
fixes a regression) the following:
7f4414b2a1
[AArch64] Generate zeroing forms of certain SVE2.2 instructions (4/11)
(https://github.com/llvm/llvm-project/pull/116830)
2474cf7ad1
[AArch64] Generate zeroing forms of certain SVE2.2 instructions (3/11)
(https://github.com/llvm/llvm-project/pull/116829)
6f285d3115
[AArch64] Generate zeroing forms of certain SVE2.2 instructions (2/11)
(https://github.com/llvm/llvm-project/pull/116828)
2b3266c170
[AArch64] Generate zeroing forms of certain SVE2.2 instructions (1/11)
(https://github.com/llvm/llvm-project/pull/116259)
1184 lines
45 KiB
LLVM
1184 lines
45 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mattr=+sve < %s | FileCheck %s
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; RUN: llc -mattr=+sve2p2 < %s | FileCheck %s -check-prefix CHECK-2p2
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; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s
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; RUN: llc -mattr=+sme2p2 -force-streaming < %s | FileCheck %s -check-prefix CHECK-2p2
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target triple = "aarch64-linux"
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define <vscale x 4 x i32> @test_fcvtzs_s32_f64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x double> %x) {
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; CHECK-LABEL: test_fcvtzs_s32_f64_x_1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.d
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_fcvtzs_s32_f64_x_1:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: fcvtzs z0.s, p0/z, z0.d
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
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ret <vscale x 4 x i32> %0
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}
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define <vscale x 4 x i32> @test_fcvtzs_s32_f64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) {
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; CHECK-LABEL: test_fcvtzs_s32_f64_x_2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtzs z0.s, p0/m, z1.d
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_fcvtzs_s32_f64_x_2:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: fcvtzs z0.s, p0/z, z1.d
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
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ret <vscale x 4 x i32> %0
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}
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define <vscale x 4 x i32> @test_fcvtzs_s32_f64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) {
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; CHECK-LABEL: test_fcvtzs_s32_f64_z:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov z0.s, #0 // =0x0
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; CHECK-NEXT: fcvtzs z0.s, p0/m, z1.d
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_fcvtzs_s32_f64_z:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: fcvtzs z0.s, p0/z, z1.d
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
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ret <vscale x 4 x i32> %0
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}
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define <vscale x 2 x i64> @test_fcvtzs_s64_f32_x_1(<vscale x 2 x i1> %pg, <vscale x 4 x float> %x) {
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; CHECK-LABEL: test_fcvtzs_s64_f32_x_1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_fcvtzs_s64_f32_x_1:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: fcvtzs z0.d, p0/z, z0.s
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f32(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 4 x float> %x)
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ret <vscale x 2 x i64> %0
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}
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define <vscale x 2 x i64> @test_fcvtzs_s64_f32_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 4 x float> %x) {
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; CHECK-LABEL: test_fcvtzs_s64_f32_x_2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.s
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_fcvtzs_s64_f32_x_2:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: fcvtzs z0.d, p0/z, z1.s
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f32(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 4 x float> %x)
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ret <vscale x 2 x i64> %0
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}
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define <vscale x 2 x i64> @test_fcvtzs_s64_f32_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 4 x float> %x) {
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; CHECK-LABEL: test_fcvtzs_s64_f32_z:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov z0.d, #0 // =0x0
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.s
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_fcvtzs_s64_f32_z:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: fcvtzs z0.d, p0/z, z1.s
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f32(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 4 x float> %x)
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ret <vscale x 2 x i64> %0
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}
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define <vscale x 4 x i32> @test_fcvtzs_s32_f16_x_1(<vscale x 4 x i1> %pg, <vscale x 8 x half> %x) {
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; CHECK-LABEL: test_fcvtzs_s32_f16_x_1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_fcvtzs_s32_f16_x_1:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: fcvtzs z0.s, p0/z, z0.h
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 8 x half> %x)
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ret <vscale x 4 x i32> %0
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}
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define <vscale x 4 x i32> @test_fcvtzs_s32_f16_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
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; CHECK-LABEL: test_fcvtzs_s32_f16_x_2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtzs z0.s, p0/m, z1.h
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_fcvtzs_s32_f16_x_2:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: fcvtzs z0.s, p0/z, z1.h
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 8 x half> %x)
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ret <vscale x 4 x i32> %0
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}
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define <vscale x 4 x i32> @test_fcvtzs_s32_f16_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
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; CHECK-LABEL: test_fcvtzs_s32_f16_z:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov z0.s, #0 // =0x0
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; CHECK-NEXT: fcvtzs z0.s, p0/m, z1.h
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_fcvtzs_s32_f16_z:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: fcvtzs z0.s, p0/z, z1.h
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 8 x half> %x)
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ret <vscale x 4 x i32> %0
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}
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define <vscale x 2 x i64> @test_fcvtzs_s64_f16_x_1(<vscale x 2 x i1> %pg, <vscale x 8 x half> %x) {
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; CHECK-LABEL: test_fcvtzs_s64_f16_x_1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_fcvtzs_s64_f16_x_1:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: fcvtzs z0.d, p0/z, z0.h
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f16(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 8 x half> %x)
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ret <vscale x 2 x i64> %0
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}
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define <vscale x 2 x i64> @test_fcvtzs_s64_f16_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
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; CHECK-LABEL: test_fcvtzs_s64_f16_x_2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.h
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_fcvtzs_s64_f16_x_2:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: fcvtzs z0.d, p0/z, z1.h
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f16(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 8 x half> %x)
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ret <vscale x 2 x i64> %0
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}
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define <vscale x 2 x i64> @test_fcvtzs_s64_f16_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
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; CHECK-LABEL: test_fcvtzs_s64_f16_z:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov z0.d, #0 // =0x0
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.h
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_fcvtzs_s64_f16_z:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: fcvtzs z0.d, p0/z, z1.h
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f16(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 8 x half> %x)
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ret <vscale x 2 x i64> %0
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}
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define <vscale x 4 x i32> @test_fcvtzu_u32_f64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x double> %x) {
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; CHECK-LABEL: test_fcvtzu_u32_f64_x_1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.d
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_fcvtzu_u32_f64_x_1:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: fcvtzu z0.s, p0/z, z0.d
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f64(<vscale x 4 x i32> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
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ret <vscale x 4 x i32> %0
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}
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define <vscale x 4 x i32> @test_fcvtzu_u32_f64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) {
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; CHECK-LABEL: test_fcvtzu_u32_f64_x_2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtzu z0.s, p0/m, z1.d
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_fcvtzu_u32_f64_x_2:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: fcvtzu z0.s, p0/z, z1.d
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f64(<vscale x 4 x i32> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
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ret <vscale x 4 x i32> %0
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}
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define <vscale x 4 x i32> @test_fcvtzu_u32_f64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) {
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; CHECK-LABEL: test_fcvtzu_u32_f64_z:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov z0.s, #0 // =0x0
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; CHECK-NEXT: fcvtzu z0.s, p0/m, z1.d
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_fcvtzu_u32_f64_z:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: fcvtzu z0.s, p0/z, z1.d
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f64(<vscale x 4 x i32> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
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ret <vscale x 4 x i32> %0
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}
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define <vscale x 2 x i64> @test_fcvtzu_u64_f32_x_1(<vscale x 2 x i1> %pg, <vscale x 4 x float> %x) {
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; CHECK-LABEL: test_fcvtzu_u64_f32_x_1:
|
|
; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.s
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; CHECK-NEXT: ret
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;
|
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; CHECK-2p2-LABEL: test_fcvtzu_u64_f32_x_1:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: fcvtzu z0.d, p0/z, z0.s
|
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; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f32(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 4 x float> %x)
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ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_fcvtzu_u64_f32_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 4 x float> %x) {
|
|
; CHECK-LABEL: test_fcvtzu_u64_f32_x_2:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.s
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_u64_f32_x_2:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzu z0.d, p0/z, z1.s
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f32(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 4 x float> %x)
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|
ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_fcvtzu_u64_f32_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 4 x float> %x) {
|
|
; CHECK-LABEL: test_fcvtzu_u64_f32_z:
|
|
; CHECK: // %bb.0: // %entry
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|
; CHECK-NEXT: mov z0.d, #0 // =0x0
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.s
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_u64_f32_z:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzu z0.d, p0/z, z1.s
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f32(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 4 x float> %x)
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ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 4 x i32> @test_fcvtzu_u32_f16_x_1(<vscale x 4 x i1> %pg, <vscale x 8 x half> %x) {
|
|
; CHECK-LABEL: test_fcvtzu_u32_f16_x_1:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_u32_f16_x_1:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzu z0.s, p0/z, z0.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f16(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 8 x half> %x)
|
|
ret <vscale x 4 x i32> %0
|
|
}
|
|
|
|
define <vscale x 4 x i32> @test_fcvtzu_u32_f16_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
|
|
; CHECK-LABEL: test_fcvtzu_u32_f16_x_2:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzu z0.s, p0/m, z1.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_u32_f16_x_2:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzu z0.s, p0/z, z1.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f16(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 8 x half> %x)
|
|
ret <vscale x 4 x i32> %0
|
|
}
|
|
|
|
define <vscale x 4 x i32> @test_fcvtzu_u32_f16_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
|
|
; CHECK-LABEL: test_fcvtzu_u32_f16_z:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: mov z0.s, #0 // =0x0
|
|
; CHECK-NEXT: fcvtzu z0.s, p0/m, z1.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_u32_f16_z:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzu z0.s, p0/z, z1.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f16(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 8 x half> %x)
|
|
ret <vscale x 4 x i32> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_fcvtzu_u64_f16_x_1(<vscale x 2 x i1> %pg, <vscale x 8 x half> %x) {
|
|
; CHECK-LABEL: test_fcvtzu_u64_f16_x_1:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_u64_f16_x_1:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzu z0.d, p0/z, z0.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f16(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 8 x half> %x)
|
|
ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_fcvtzu_u64_f16_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
|
|
; CHECK-LABEL: test_fcvtzu_u64_f16_x_2:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_u64_f16_x_2:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzu z0.d, p0/z, z1.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f16(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 8 x half> %x)
|
|
ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_fcvtzu_u64_f16_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
|
|
; CHECK-LABEL: test_fcvtzu_u64_f16_z:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: mov z0.d, #0 // =0x0
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_u64_f16_z:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzu z0.d, p0/z, z1.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f16(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 8 x half> %x)
|
|
ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
|
|
define <vscale x 8 x i16> @test_svcvt_s16_f16_x_1(<vscale x 8 x i1> %pg, <vscale x 8 x half> %x) {
|
|
; CHECK-LABEL: test_svcvt_s16_f16_x_1:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzs z0.h, p0/m, z0.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_svcvt_s16_f16_x_1:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzs z0.h, p0/z, z0.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
|
|
ret <vscale x 8 x i16> %0
|
|
}
|
|
|
|
define <vscale x 8 x i16> @test_svcvt_s16_f16_x_2(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
|
|
; CHECK-LABEL: test_svcvt_s16_f16_x_2:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: movprfx z0, z1
|
|
; CHECK-NEXT: fcvtzs z0.h, p0/m, z1.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_svcvt_s16_f16_x_2:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzs z0.h, p0/z, z1.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
|
|
ret <vscale x 8 x i16> %0
|
|
}
|
|
|
|
define <vscale x 8 x i16> @test_svcvt_s16_f16_z(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
|
|
; CHECK-LABEL: test_svcvt_s16_f16_z:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: mov z0.h, #0 // =0x0
|
|
; CHECK-NEXT: fcvtzs z0.h, p0/m, z1.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_svcvt_s16_f16_z:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzs z0.h, p0/z, z1.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
|
|
ret <vscale x 8 x i16> %0
|
|
}
|
|
|
|
define <vscale x 8 x i16> @test_svcvt_u16_f16_x_1(<vscale x 8 x i1> %pg, <vscale x 8 x half> %x) {
|
|
; CHECK-LABEL: test_svcvt_u16_f16_x_1:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzu z0.h, p0/m, z0.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_svcvt_u16_f16_x_1:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzu z0.h, p0/z, z0.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
|
|
ret <vscale x 8 x i16> %0
|
|
}
|
|
|
|
define <vscale x 8 x i16> @test_svcvt_u16_f16_x_2(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
|
|
; CHECK-LABEL: test_svcvt_u16_f16_x_2:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: movprfx z0, z1
|
|
; CHECK-NEXT: fcvtzu z0.h, p0/m, z1.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_svcvt_u16_f16_x_2:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzu z0.h, p0/z, z1.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
|
|
ret <vscale x 8 x i16> %0
|
|
}
|
|
|
|
define <vscale x 8 x i16> @test_svcvt_u16_f16_z(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
|
|
; CHECK-LABEL: test_svcvt_u16_f16_z:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: mov z0.h, #0 // =0x0
|
|
; CHECK-NEXT: fcvtzu z0.h, p0/m, z1.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_svcvt_u16_f16_z:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzu z0.h, p0/z, z1.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
|
|
ret <vscale x 8 x i16> %0
|
|
}
|
|
|
|
define <vscale x 4 x i32> @test_svcvt_s32_f32_x_1(<vscale x 4 x i1> %pg, <vscale x 4 x float> %x) {
|
|
; CHECK-LABEL: test_svcvt_s32_f32_x_1:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_svcvt_s32_f32_x_1:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzs z0.s, p0/z, z0.s
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
|
|
ret <vscale x 4 x i32> %0
|
|
}
|
|
|
|
define <vscale x 4 x i32> @test_svcvt_s32_f32_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x float> %x) {
|
|
; CHECK-LABEL: test_svcvt_s32_f32_x_2:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: movprfx z0, z1
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z1.s
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_svcvt_s32_f32_x_2:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzs z0.s, p0/z, z1.s
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
|
|
ret <vscale x 4 x i32> %0
|
|
}
|
|
|
|
define <vscale x 4 x i32> @test_svcvt_s32_f32_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x float> %x) {
|
|
; CHECK-LABEL: test_svcvt_s32_f32_z:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: mov z0.s, #0 // =0x0
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z1.s
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_svcvt_s32_f32_z:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzs z0.s, p0/z, z1.s
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
|
|
ret <vscale x 4 x i32> %0
|
|
}
|
|
|
|
define <vscale x 4 x i32> @test_svcvt_u32_f32_x_1(<vscale x 4 x i1> %pg, <vscale x 4 x float> %x) {
|
|
; CHECK-LABEL: test_svcvt_u32_f32_x_1:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_svcvt_u32_f32_x_1:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzu z0.s, p0/z, z0.s
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.nxv4i32.nxv4f32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
|
|
ret <vscale x 4 x i32> %0
|
|
}
|
|
|
|
define <vscale x 4 x i32> @test_svcvt_u32_f32_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x float> %x) {
|
|
; CHECK-LABEL: test_svcvt_u32_f32_x_2:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: movprfx z0, z1
|
|
; CHECK-NEXT: fcvtzu z0.s, p0/m, z1.s
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_svcvt_u32_f32_x_2:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzu z0.s, p0/z, z1.s
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.nxv4i32.nxv4f32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
|
|
ret <vscale x 4 x i32> %0
|
|
}
|
|
|
|
define <vscale x 4 x i32> @test_svcvt_u32_f32_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x float> %x) {
|
|
; CHECK-LABEL: test_svcvt_u32_f32_z:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: mov z0.s, #0 // =0x0
|
|
; CHECK-NEXT: fcvtzu z0.s, p0/m, z1.s
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_svcvt_u32_f32_z:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzu z0.s, p0/z, z1.s
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.nxv4i32.nxv4f32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
|
|
ret <vscale x 4 x i32> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_svcvt_s64_f64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x double> %x) {
|
|
; CHECK-LABEL: test_svcvt_s64_f64_x_1:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_svcvt_s64_f64_x_1:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzs z0.d, p0/z, z0.d
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.nxv2i64.nxv2f64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
|
|
ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_svcvt_s64_f64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) {
|
|
; CHECK-LABEL: test_svcvt_s64_f64_x_2:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: movprfx z0, z1
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.d
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_svcvt_s64_f64_x_2:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzs z0.d, p0/z, z1.d
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.nxv2i64.nxv2f64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
|
|
ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_svcvt_s64_f64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) {
|
|
; CHECK-LABEL: test_svcvt_s64_f64_z:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: mov z0.d, #0 // =0x0
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.d
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_svcvt_s64_f64_z:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzs z0.d, p0/z, z1.d
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.nxv2i64.nxv2f64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
|
|
ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_svcvt_u64_f64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x double> %x) {
|
|
; CHECK-LABEL: test_svcvt_u64_f64_x_1:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_svcvt_u64_f64_x_1:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzu z0.d, p0/z, z0.d
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.nxv2i64.nxv2f64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
|
|
ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_svcvt_u64_f64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) {
|
|
; CHECK-LABEL: test_svcvt_u64_f64_x_2:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: movprfx z0, z1
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.d
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_svcvt_u64_f64_x_2:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzu z0.d, p0/z, z1.d
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.nxv2i64.nxv2f64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
|
|
ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_svcvt_u64_f64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) {
|
|
; CHECK-LABEL: test_svcvt_u64_f64_z:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: mov z0.d, #0 // =0x0
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.d
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_svcvt_u64_f64_z:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: fcvtzu z0.d, p0/z, z1.d
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.nxv2i64.nxv2f64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
|
|
ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 4 x i32> @test_fcvtzs_i32_f64_ptrue_u(double %z0, <vscale x 2 x double> %x) {
|
|
; CHECK-LABEL: test_fcvtzs_i32_f64_ptrue_u:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z1.d
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzs_i32_f64_ptrue_u:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.d
|
|
; CHECK-2p2-NEXT: fcvtzs z0.s, p0/z, z1.d
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
|
|
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
|
|
ret <vscale x 4 x i32> %0
|
|
}
|
|
|
|
define <vscale x 4 x i32> @test_fcvtzs_i32_f64_ptrue(double %z0, <vscale x 4 x i32> %x, <vscale x 2 x double> %y) {
|
|
; CHECK-LABEL: test_fcvtzs_i32_f64_ptrue:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: mov z0.d, z1.d
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z2.d
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzs_i32_f64_ptrue:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.d
|
|
; CHECK-2p2-NEXT: fcvtzs z0.s, p0/z, z2.d
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
|
|
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32> %x, <vscale x 2 x i1> %pg, <vscale x 2 x double> %y)
|
|
ret <vscale x 4 x i32> %0
|
|
}
|
|
|
|
define <vscale x 4 x i32> @test_fcvtzu_i32_f64_ptrue_u(double %z0, <vscale x 2 x double> %x) {
|
|
; CHECK-LABEL: test_fcvtzu_i32_f64_ptrue_u:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: fcvtzu z0.s, p0/m, z1.d
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_i32_f64_ptrue_u:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.d
|
|
; CHECK-2p2-NEXT: fcvtzu z0.s, p0/z, z1.d
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
|
|
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f64(<vscale x 4 x i32> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
|
|
ret <vscale x 4 x i32> %0
|
|
}
|
|
|
|
define <vscale x 4 x i32> @test_fcvtzu_i32_f64_ptrue(double %z0, <vscale x 4 x i32> %x, <vscale x 2 x double> %y) {
|
|
; CHECK-LABEL: test_fcvtzu_i32_f64_ptrue:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: mov z0.d, z1.d
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: fcvtzu z0.s, p0/m, z2.d
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_i32_f64_ptrue:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.d
|
|
; CHECK-2p2-NEXT: fcvtzu z0.s, p0/z, z2.d
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
|
|
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f64(<vscale x 4 x i32> %x, <vscale x 2 x i1> %pg, <vscale x 2 x double> %y)
|
|
ret <vscale x 4 x i32> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_fcvtzs_i64_f32_ptrue_u(double %z0, <vscale x 4 x float> %x) {
|
|
; CHECK-LABEL: test_fcvtzs_i64_f32_ptrue_u:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.s
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzs_i64_f32_ptrue_u:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.d
|
|
; CHECK-2p2-NEXT: fcvtzs z0.d, p0/z, z1.s
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f32(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 4 x float> %x)
|
|
ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_fcvtzs_i64_f32_ptrue(double %z0, <vscale x 2 x i64> %x, <vscale x 4 x float> %y) {
|
|
; CHECK-LABEL: test_fcvtzs_i64_f32_ptrue:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: mov z0.d, z1.d
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z2.s
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzs_i64_f32_ptrue:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.d
|
|
; CHECK-2p2-NEXT: fcvtzs z0.d, p0/z, z2.s
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f32(<vscale x 2 x i64> %x, <vscale x 2 x i1> %pg, <vscale x 4 x float> %y)
|
|
ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_fcvtzu_i64_f32_ptrue_u(double %z0, <vscale x 4 x float> %x) {
|
|
; CHECK-LABEL: test_fcvtzu_i64_f32_ptrue_u:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.s
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_i64_f32_ptrue_u:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.d
|
|
; CHECK-2p2-NEXT: fcvtzu z0.d, p0/z, z1.s
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f32(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 4 x float> %x)
|
|
ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_fcvtzu_i64_f32_ptrue(double %z0, <vscale x 2 x i64> %x, <vscale x 4 x float> %y) {
|
|
; CHECK-LABEL: test_fcvtzu_i64_f32_ptrue:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: mov z0.d, z1.d
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z2.s
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_i64_f32_ptrue:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.d
|
|
; CHECK-2p2-NEXT: fcvtzu z0.d, p0/z, z2.s
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f32(<vscale x 2 x i64> %x, <vscale x 2 x i1> %pg, <vscale x 4 x float> %y)
|
|
ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 4 x i32> @test_fcvtzs_i32_f16_ptrue_u(double %z0, <vscale x 8 x half> %x) {
|
|
; CHECK-LABEL: test_fcvtzs_i32_f16_ptrue_u:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: ptrue p0.s
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z1.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzs_i32_f16_ptrue_u:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.s
|
|
; CHECK-2p2-NEXT: fcvtzs z0.s, p0/z, z1.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
|
|
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 8 x half> %x)
|
|
ret <vscale x 4 x i32> %0
|
|
}
|
|
|
|
define <vscale x 4 x i32> @test_fcvtzs_i32_f16_ptrue(double %z0, <vscale x 4 x i32> %x, <vscale x 8 x half> %y) {
|
|
; CHECK-LABEL: test_fcvtzs_i32_f16_ptrue:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: mov z0.d, z1.d
|
|
; CHECK-NEXT: ptrue p0.s
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z2.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzs_i32_f16_ptrue:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.s
|
|
; CHECK-2p2-NEXT: fcvtzs z0.s, p0/z, z2.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
|
|
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> %x, <vscale x 4 x i1> %pg, <vscale x 8 x half> %y)
|
|
ret <vscale x 4 x i32> %0
|
|
}
|
|
|
|
define <vscale x 4 x i32> @test_fcvtzu_i32_f16_ptrue_u(double %z0, <vscale x 8 x half> %x) {
|
|
; CHECK-LABEL: test_fcvtzu_i32_f16_ptrue_u:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: ptrue p0.s
|
|
; CHECK-NEXT: fcvtzu z0.s, p0/m, z1.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_i32_f16_ptrue_u:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.s
|
|
; CHECK-2p2-NEXT: fcvtzu z0.s, p0/z, z1.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
|
|
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f16(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 8 x half> %x)
|
|
ret <vscale x 4 x i32> %0
|
|
}
|
|
|
|
define <vscale x 4 x i32> @test_fcvtzu_i32_f16_ptrue(double %z0, <vscale x 4 x i32> %x, <vscale x 8 x half> %y) {
|
|
; CHECK-LABEL: test_fcvtzu_i32_f16_ptrue:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: mov z0.d, z1.d
|
|
; CHECK-NEXT: ptrue p0.s
|
|
; CHECK-NEXT: fcvtzu z0.s, p0/m, z2.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_i32_f16_ptrue:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.s
|
|
; CHECK-2p2-NEXT: fcvtzu z0.s, p0/z, z2.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
|
|
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f16(<vscale x 4 x i32> %x, <vscale x 4 x i1> %pg, <vscale x 8 x half> %y)
|
|
ret <vscale x 4 x i32> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_fcvtzs_i64_f16_ptrue_u(double %z0, <vscale x 8 x half> %x) {
|
|
; CHECK-LABEL: test_fcvtzs_i64_f16_ptrue_u:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzs_i64_f16_ptrue_u:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.d
|
|
; CHECK-2p2-NEXT: fcvtzs z0.d, p0/z, z1.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f16(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 8 x half> %x)
|
|
ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_fcvtzs_i64_f16_ptrue(double %z0, <vscale x 2 x i64> %x, <vscale x 8 x half> %y) {
|
|
; CHECK-LABEL: test_fcvtzs_i64_f16_ptrue:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: mov z0.d, z1.d
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z2.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzs_i64_f16_ptrue:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.d
|
|
; CHECK-2p2-NEXT: fcvtzs z0.d, p0/z, z2.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f16(<vscale x 2 x i64> %x, <vscale x 2 x i1> %pg, <vscale x 8 x half> %y)
|
|
ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_fcvtzu_i64_f16_ptrue_u(double %z0, <vscale x 8 x half> %x) {
|
|
; CHECK-LABEL: test_fcvtzu_i64_f16_ptrue_u:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_i64_f16_ptrue_u:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.d
|
|
; CHECK-2p2-NEXT: fcvtzu z0.d, p0/z, z1.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f16(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 8 x half> %x)
|
|
ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_fcvtzu_i64_f16_ptrue(double %z0, <vscale x 2 x i64> %x, <vscale x 8 x half> %y) {
|
|
; CHECK-LABEL: test_fcvtzu_i64_f16_ptrue:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: mov z0.d, z1.d
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z2.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_i64_f16_ptrue:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.d
|
|
; CHECK-2p2-NEXT: fcvtzu z0.d, p0/z, z2.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f16(<vscale x 2 x i64> %x, <vscale x 2 x i1> %pg, <vscale x 8 x half> %y)
|
|
ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 8 x i16> @test_fcvtzs_i16_f16_ptrue_u(double %z0, <vscale x 8 x half> %x) {
|
|
; CHECK-LABEL: test_fcvtzs_i16_f16_ptrue_u:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: ptrue p0.h
|
|
; CHECK-NEXT: movprfx z0, z1
|
|
; CHECK-NEXT: fcvtzs z0.h, p0/m, z1.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzs_i16_f16_ptrue_u:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.h
|
|
; CHECK-2p2-NEXT: fcvtzs z0.h, p0/z, z1.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
|
|
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
|
|
ret <vscale x 8 x i16> %0
|
|
}
|
|
|
|
define <vscale x 8 x i16> @test_fcvtzs_i16_f16_ptrue(double %z0, <vscale x 8 x i16> %x, <vscale x 8 x half> %y) {
|
|
; CHECK-LABEL: test_fcvtzs_i16_f16_ptrue:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: ptrue p0.h
|
|
; CHECK-NEXT: movprfx z0, z2
|
|
; CHECK-NEXT: fcvtzs z0.h, p0/m, z2.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzs_i16_f16_ptrue:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.h
|
|
; CHECK-2p2-NEXT: fcvtzs z0.h, p0/z, z2.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
|
|
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> %x, <vscale x 8 x i1> %pg, <vscale x 8 x half> %y)
|
|
ret <vscale x 8 x i16> %0
|
|
}
|
|
|
|
define <vscale x 8 x i16> @test_fcvtzu_i16_f16_ptrue_u(double %z0, <vscale x 8 x half> %x) {
|
|
; CHECK-LABEL: test_fcvtzu_i16_f16_ptrue_u:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: ptrue p0.h
|
|
; CHECK-NEXT: movprfx z0, z1
|
|
; CHECK-NEXT: fcvtzu z0.h, p0/m, z1.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_i16_f16_ptrue_u:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.h
|
|
; CHECK-2p2-NEXT: fcvtzu z0.h, p0/z, z1.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
|
|
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
|
|
ret <vscale x 8 x i16> %0
|
|
}
|
|
|
|
define <vscale x 8 x i16> @test_fcvtzu_i16_f16_ptrue(double %z0, <vscale x 8 x i16> %x, <vscale x 8 x half> %y) {
|
|
; CHECK-LABEL: test_fcvtzu_i16_f16_ptrue:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: ptrue p0.h
|
|
; CHECK-NEXT: movprfx z0, z2
|
|
; CHECK-NEXT: fcvtzu z0.h, p0/m, z2.h
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_i16_f16_ptrue:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.h
|
|
; CHECK-2p2-NEXT: fcvtzu z0.h, p0/z, z2.h
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
|
|
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16> %x, <vscale x 8 x i1> %pg, <vscale x 8 x half> %y)
|
|
ret <vscale x 8 x i16> %0
|
|
}
|
|
|
|
define <vscale x 4 x i32> @test_fcvtzs_i32_f32_ptrue_u(double %z0, <vscale x 4 x float> %x) {
|
|
; CHECK-LABEL: test_fcvtzs_i32_f32_ptrue_u:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: ptrue p0.s
|
|
; CHECK-NEXT: movprfx z0, z1
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z1.s
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzs_i32_f32_ptrue_u:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.s
|
|
; CHECK-2p2-NEXT: fcvtzs z0.s, p0/z, z1.s
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
|
|
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
|
|
ret <vscale x 4 x i32> %0
|
|
}
|
|
|
|
define <vscale x 4 x i32> @test_fcvtzs_i32_f32_ptrue(double %z0, <vscale x 4 x i32> %x, <vscale x 4 x float> %y) {
|
|
; CHECK-LABEL: test_fcvtzs_i32_f32_ptrue:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: ptrue p0.s
|
|
; CHECK-NEXT: movprfx z0, z2
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z2.s
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzs_i32_f32_ptrue:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.s
|
|
; CHECK-2p2-NEXT: fcvtzs z0.s, p0/z, z2.s
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
|
|
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32(<vscale x 4 x i32> %x, <vscale x 4 x i1> %pg, <vscale x 4 x float> %y)
|
|
ret <vscale x 4 x i32> %0
|
|
}
|
|
|
|
define <vscale x 4 x i32> @test_fcvtzu_i32_f32_ptrue_u(double %z0, <vscale x 4 x float> %x) {
|
|
; CHECK-LABEL: test_fcvtzu_i32_f32_ptrue_u:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: ptrue p0.s
|
|
; CHECK-NEXT: movprfx z0, z1
|
|
; CHECK-NEXT: fcvtzu z0.s, p0/m, z1.s
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_i32_f32_ptrue_u:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.s
|
|
; CHECK-2p2-NEXT: fcvtzu z0.s, p0/z, z1.s
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
|
|
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.nxv4i32.nxv4f32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
|
|
ret <vscale x 4 x i32> %0
|
|
}
|
|
|
|
define <vscale x 4 x i32> @test_fcvtzu_i32_f32_ptrue(double %z0, <vscale x 4 x i32> %x, <vscale x 4 x float> %y) {
|
|
; CHECK-LABEL: test_fcvtzu_i32_f32_ptrue:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: ptrue p0.s
|
|
; CHECK-NEXT: movprfx z0, z2
|
|
; CHECK-NEXT: fcvtzu z0.s, p0/m, z2.s
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_i32_f32_ptrue:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.s
|
|
; CHECK-2p2-NEXT: fcvtzu z0.s, p0/z, z2.s
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
|
|
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.nxv4i32.nxv4f32(<vscale x 4 x i32> %x, <vscale x 4 x i1> %pg, <vscale x 4 x float> %y)
|
|
ret <vscale x 4 x i32> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_fcvtzs_i64_f64_ptrue_u(double %z0, <vscale x 2 x double> %x) {
|
|
; CHECK-LABEL: test_fcvtzs_i64_f64_ptrue_u:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: movprfx z0, z1
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.d
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzs_i64_f64_ptrue_u:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.d
|
|
; CHECK-2p2-NEXT: fcvtzs z0.d, p0/z, z1.d
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.nxv2i64.nxv2f64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
|
|
ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_fcvtzs_i64_f64_ptrue(double %z0, <vscale x 2 x i64> %x, <vscale x 2 x double> %y) {
|
|
; CHECK-LABEL: test_fcvtzs_i64_f64_ptrue:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: movprfx z0, z2
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z2.d
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzs_i64_f64_ptrue:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.d
|
|
; CHECK-2p2-NEXT: fcvtzs z0.d, p0/z, z2.d
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.nxv2i64.nxv2f64(<vscale x 2 x i64> %x, <vscale x 2 x i1> %pg, <vscale x 2 x double> %y)
|
|
ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_fcvtzu_i64_f64_ptrue_u(double %z0, <vscale x 2 x double> %x) {
|
|
; CHECK-LABEL: test_fcvtzu_i64_f64_ptrue_u:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: movprfx z0, z1
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.d
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_i64_f64_ptrue_u:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.d
|
|
; CHECK-2p2-NEXT: fcvtzu z0.d, p0/z, z1.d
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.nxv2i64.nxv2f64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
|
|
ret <vscale x 2 x i64> %0
|
|
}
|
|
|
|
define <vscale x 2 x i64> @test_fcvtzu_i64_f64_ptrue(double %z0, <vscale x 2 x i64> %x, <vscale x 2 x double> %y) {
|
|
; CHECK-LABEL: test_fcvtzu_i64_f64_ptrue:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: movprfx z0, z2
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z2.d
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-2p2-LABEL: test_fcvtzu_i64_f64_ptrue:
|
|
; CHECK-2p2: // %bb.0: // %entry
|
|
; CHECK-2p2-NEXT: ptrue p0.d
|
|
; CHECK-2p2-NEXT: fcvtzu z0.d, p0/z, z2.d
|
|
; CHECK-2p2-NEXT: ret
|
|
entry:
|
|
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
|
|
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.nxv2i64.nxv2f64(<vscale x 2 x i64> %x, <vscale x 2 x i1> %pg, <vscale x 2 x double> %y)
|
|
ret <vscale x 2 x i64> %0
|
|
}
|