b856e77b2d
Targets affected: - NVPTX and BPF: set to 64 bits. - ARC, Lanai, and MSP430: set to 0 (they don't implement atomics). Those which didn't yet add AtomicExpandPass to their pass pipeline now do so. This will result in larger atomic operations getting expanded to `__atomic_*` libcalls via AtomicExpandPass. On all these targets, this now matches what Clang already does in the frontend. The only targets which do not configure AtomicExpandPass now are: - DirectX and SPIRV: they aren't normal backends. - AVR: a single-cpu architecture with no privileged/user divide, which could implement all atomics by disabling/enabling interrupts, regardless of size/alignment. Will be addressed by future work.
12 lines
336 B
LLVM
12 lines
336 B
LLVM
; RUN: llc -mtriple=msp430 < %s | FileCheck %s
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; Native atomics are unsupported, so all are oversize.
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define void @test(ptr %a) nounwind {
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; CHECK-LABEL: test:
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; CHECK: call #__atomic_load_1
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; CHECK: call #__atomic_store_1
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%1 = load atomic i8, ptr %a monotonic, align 16
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store atomic i8 %1, ptr %a monotonic, align 16
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ret void
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}
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