97982a8c60
This patch adds CFI instructions in the function epilogue. Before patch: addi sp, s0, -32 ld ra, 24(sp) # 8-byte Folded Reload ld s0, 16(sp) # 8-byte Folded Reload ld s1, 8(sp) # 8-byte Folded Reload addi sp, sp, 32 ret After patch: addi sp, s0, -32 .cfi_def_cfa sp, 32 ld ra, 24(sp) # 8-byte Folded Reload ld s0, 16(sp) # 8-byte Folded Reload ld s1, 8(sp) # 8-byte Folded Reload .cfi_restore ra .cfi_restore s0 .cfi_restore s1 addi sp, sp, 32 .cfi_def_cfa_offset 0 ret This functionality is already present in `riscv-gcc`, but it’s not in `clang` and this slightly impairs the `lldb` debugging experience, e.g. backtrace.
111 lines
3.4 KiB
LLVM
111 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32F %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64F %s
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; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32F %s
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; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64F %s
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@gf = external global float
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define float @constraint_f_float(float %a) nounwind {
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; RV32F-LABEL: constraint_f_float:
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; RV32F: # %bb.0:
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; RV32F-NEXT: lui a1, %hi(gf)
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; RV32F-NEXT: flw fa5, %lo(gf)(a1)
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; RV32F-NEXT: fmv.w.x fa4, a0
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; RV32F-NEXT: #APP
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; RV32F-NEXT: fadd.s fa5, fa4, fa5
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; RV32F-NEXT: #NO_APP
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; RV32F-NEXT: fmv.x.w a0, fa5
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; RV32F-NEXT: ret
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;
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; RV64F-LABEL: constraint_f_float:
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; RV64F: # %bb.0:
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; RV64F-NEXT: lui a1, %hi(gf)
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; RV64F-NEXT: flw fa5, %lo(gf)(a1)
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; RV64F-NEXT: fmv.w.x fa4, a0
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; RV64F-NEXT: #APP
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; RV64F-NEXT: fadd.s fa5, fa4, fa5
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; RV64F-NEXT: #NO_APP
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; RV64F-NEXT: fmv.x.w a0, fa5
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; RV64F-NEXT: ret
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%1 = load float, ptr @gf
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%2 = tail call float asm "fadd.s $0, $1, $2", "=f,f,f"(float %a, float %1)
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ret float %2
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}
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define float @constraint_cf_float(float %a) nounwind {
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; RV32F-LABEL: constraint_cf_float:
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; RV32F: # %bb.0:
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; RV32F-NEXT: lui a1, %hi(gf)
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; RV32F-NEXT: flw fa5, %lo(gf)(a1)
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; RV32F-NEXT: fmv.w.x fa4, a0
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; RV32F-NEXT: #APP
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; RV32F-NEXT: fadd.s fa5, fa4, fa5
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; RV32F-NEXT: #NO_APP
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; RV32F-NEXT: fmv.x.w a0, fa5
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; RV32F-NEXT: ret
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;
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; RV64F-LABEL: constraint_cf_float:
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; RV64F: # %bb.0:
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; RV64F-NEXT: lui a1, %hi(gf)
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; RV64F-NEXT: flw fa5, %lo(gf)(a1)
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; RV64F-NEXT: fmv.w.x fa4, a0
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; RV64F-NEXT: #APP
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; RV64F-NEXT: fadd.s fa5, fa4, fa5
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; RV64F-NEXT: #NO_APP
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; RV64F-NEXT: fmv.x.w a0, fa5
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; RV64F-NEXT: ret
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%1 = load float, ptr @gf
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%2 = tail call float asm "fadd.s $0, $1, $2", "=^cf,cf,cf"(float %a, float %1)
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ret float %2
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}
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define float @constraint_f_float_abi_name(float %a) nounwind {
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; RV32F-LABEL: constraint_f_float_abi_name:
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; RV32F: # %bb.0:
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; RV32F-NEXT: lui a1, %hi(gf)
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; RV32F-NEXT: flw fs0, %lo(gf)(a1)
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; RV32F-NEXT: fmv.w.x fa0, a0
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; RV32F-NEXT: #APP
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; RV32F-NEXT: fadd.s ft0, fa0, fs0
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; RV32F-NEXT: #NO_APP
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; RV32F-NEXT: fmv.x.w a0, ft0
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; RV32F-NEXT: ret
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;
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; RV64F-LABEL: constraint_f_float_abi_name:
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; RV64F: # %bb.0:
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; RV64F-NEXT: lui a1, %hi(gf)
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; RV64F-NEXT: flw fs0, %lo(gf)(a1)
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; RV64F-NEXT: fmv.w.x fa0, a0
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; RV64F-NEXT: #APP
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; RV64F-NEXT: fadd.s ft0, fa0, fs0
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; RV64F-NEXT: #NO_APP
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; RV64F-NEXT: fmv.x.w a0, ft0
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; RV64F-NEXT: ret
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%1 = load float, ptr @gf
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%2 = tail call float asm "fadd.s $0, $1, $2", "={ft0},{fa0},{fs0}"(float %a, float %1)
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ret float %2
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}
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define float @constraint_gpr(float %x) {
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; RV32F-LABEL: constraint_gpr:
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; RV32F: # %bb.0:
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; RV32F-NEXT: #APP
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; RV32F-NEXT: mv a0, a0
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; RV32F-NEXT: #NO_APP
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; RV32F-NEXT: ret
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;
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; RV64F-LABEL: constraint_gpr:
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; RV64F: # %bb.0:
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; RV64F-NEXT: #APP
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; RV64F-NEXT: mv a0, a0
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; RV64F-NEXT: #NO_APP
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; RV64F-NEXT: ret
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%1 = tail call float asm sideeffect alignstack "mv $0, $1", "={x10},{x10}"(float %x)
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ret float %1
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}
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