70a64fe7b1
This extension does not appear to be on its way to ratification. Out of the unratified bitmanip extensions, this one had the largest impact on the compiler. Posting this patch to start a discussion about whether we should remove these extensions. We'll talk more at the RISC-V sync meeting this Thursday. Reviewed By: asb, reames Differential Revision: https://reviews.llvm.org/D133834
32 lines
905 B
LLVM
32 lines
905 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
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; RV32I-LABEL: bare_select:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a3, a0, 1
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: bnez a3, .LBB0_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: .LBB0_2:
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; RV32I-NEXT: ret
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%1 = select i1 %a, i32 %b, i32 %c
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ret i32 %1
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}
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define float @bare_select_float(i1 %a, float %b, float %c) nounwind {
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; RV32I-LABEL: bare_select_float:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a3, a0, 1
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: bnez a3, .LBB1_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: .LBB1_2:
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; RV32I-NEXT: ret
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%1 = select i1 %a, float %b, float %c
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ret float %1
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}
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