cba70550cc
The "topological" sorting was behaving incorrectly in some cases: the exit of a loop could have a lower rank than a node in the loop. This causes issues when structurizing some patterns, and also codegen issues as we could generate BBs in the incorrect order in regard to the SPIR-V spec. Fixing this ordering alone broke other parts of the structurizer, which by luck worked. Had to fix those. Added more test cases, especially to test basic patterns. I also needed to tweak/disable some tests for 2 reasons: - SPIR-V now required reg2mem/mem2reg to run. Meaning dead stores are optimized away. Some tests require tweaks to avoid having the whole function removed. - Mem2Reg will generate variable & load/stores. This generates G_BITCAST in several cases. And there is currently something wrong we do with G_BITCAST which causes MIR verifier to complain. Until this is resolved, I disabled -verify-machineinstrs flag on those tests. --------- Signed-off-by: Nathan Gauër <brioche@google.com>
91 lines
3.6 KiB
LLVM
91 lines
3.6 KiB
LLVM
; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s --match-full-lines
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %}
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target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"
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target triple = "spirv-unknown-vulkan-compute"
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define internal spir_func void @main() #0 {
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; CHECK-DAG: OpName %[[#idx:]] "idx"
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; CHECK-DAG: OpDecorate %[[#builtin:]] BuiltIn SubgroupLocalInvocationId
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; CHECK-DAG: %[[#int_ty:]] = OpTypeInt 32 0
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; CHECK-DAG: %[[#bool_ty:]] = OpTypeBool
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; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#int_ty]] 0
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; CHECK-DAG: %[[#int_10:]] = OpConstant %[[#int_ty]] 10
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; CHECK: %[[#entry:]] = OpLabel
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; CHECK: %[[#idx]] = OpVariable %[[#]] Function
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; CHECK: OpStore %[[#idx]] %[[#int_0]] Aligned 4
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; CHECK: OpBranch %[[#while_cond:]]
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entry:
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%0 = call token @llvm.experimental.convergence.entry()
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%idx = alloca i32, align 4
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store i32 0, ptr %idx, align 4
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br label %while.cond
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; CHECK: %[[#while_cond]] = OpLabel
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; CHECK: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#idx]] Aligned 4
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; CHECK: %[[#cmp:]] = OpINotEqual %[[#bool_ty]] %[[#tmp]] %[[#int_10]]
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; CHECK: OpLoopMerge %[[#new_end:]] %[[#if_end:]] None
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; CHECK: OpBranchConditional %[[#cmp]] %[[#while_body:]] %[[#new_end]]
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while.cond:
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%1 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ]
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%2 = load i32, ptr %idx, align 4
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%cmp = icmp ne i32 %2, 10
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br i1 %cmp, label %while.body, label %while.end
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; CHECK: %[[#while_body]] = OpLabel
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; CHECK-NEXT: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#builtin]] Aligned 1
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; CHECK-NEXT: OpStore %[[#idx]] %[[#tmp]] Aligned 4
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; CHECK-NEXT: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#idx]] Aligned 4
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; CHECK-NEXT: %[[#cmp1:]] = OpIEqual %[[#bool_ty]] %[[#tmp]] %[[#int_0]]
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; CHECK: OpBranchConditional %[[#cmp1]] %[[#if_then:]] %[[#if_end]]
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while.body:
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%3 = call i32 @__hlsl_wave_get_lane_index() [ "convergencectrl"(token %1) ]
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store i32 %3, ptr %idx, align 4
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%4 = load i32, ptr %idx, align 4
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%cmp1 = icmp eq i32 %4, 0
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br i1 %cmp1, label %if.then, label %if.end
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; CHECK: %[[#if_end]] = OpLabel
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; CHECK: OpBranch %[[#while_cond]]
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; CHECK: %[[#if_then]] = OpLabel
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; CHECK: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#builtin]] Aligned 1
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; CHECK: OpStore %[[#idx]] %[[#tmp]] Aligned 4
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; CHECK: OpBranch %[[#new_end]]
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if.then:
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%5 = call i32 @__hlsl_wave_get_lane_index() [ "convergencectrl"(token %1) ]
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store i32 %5, ptr %idx, align 4
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br label %while.end
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if.end:
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br label %while.cond
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; CHECK: %[[#new_end]] = OpLabel
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; CHECK: OpBranch %[[#while_end:]]
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; CHECK: %[[#while_end]] = OpLabel
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; CHECK: OpReturn
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while.end:
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ret void
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}
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declare token @llvm.experimental.convergence.entry() #2
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declare token @llvm.experimental.convergence.loop() #2
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declare i32 @__hlsl_wave_get_lane_index() #3
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attributes #0 = { convergent noinline norecurse nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
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attributes #1 = { convergent norecurse "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
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attributes #2 = { convergent nocallback nofree nosync nounwind willreturn memory(none) }
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attributes #3 = { convergent }
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!llvm.module.flags = !{!0, !1}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 4, !"dx.disable_optimizations", i32 1}
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