21 lines
410 B
Systemverilog
21 lines
410 B
Systemverilog
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module spram_big
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(
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input wire clk,
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input wire [3:0] we[4],
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input wire [15:0] addr,
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input wire [15:0] data_in[4],
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output wire [15:0] data_out
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);
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wire [15:0] datas_out[4];
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genvar i;
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generate
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for (i = 0; i < 4; i = i + 1) begin
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spram spram_inst(.clk(clk), .we(we[i]), .addr(addr[15:2]), .data_in(data_in[i]), .data_out(datas_out[i]));
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end
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endgenerate
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assign data_out = datas_out[addr[1:0]];
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endmodule
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