20 lines
250 B
Systemverilog
20 lines
250 B
Systemverilog
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module top
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(
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input wire clk,
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input wire start,
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output wire [7:0] data
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);
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reg [7:0] data_r;
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always_ff @(posedge clk) begin
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data_r <= data_r + 1;
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if (data_r < 16 || data_r > 235) begin
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data_r <= 16;
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end
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end
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assign data = data_r;
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endmodule
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