69 lines
1.3 KiB
Systemverilog
69 lines
1.3 KiB
Systemverilog
module top
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(
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input wire clk,
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input wire dir,
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inout wire req,
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output wire fin,
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inout wire [7:0] data
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);
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reg [3:0] clk_div_8_counter;
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wire clk_div_8;
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reg dir_last;
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reg req_last;
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reg req_r;
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reg [7:0] waddr;
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reg [7:0] raddr;
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wire [7:0] command;
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ram command_buffer(.wclk(clk), .rclk(clk), .waddr(waddr), .raddr(raddr), .data_in(data), .write_en(dir && req), .data_out(command));
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wire [6:0] x[4];
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wire [6:0] y[4];
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coords #(.POS_COUNT(4)) coords_inst(.clk(clk_div_8), .rst(!req_r), .x(x), .y(y), .finished(fin));
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wire [2:0] iters[4];
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wire [7:0] data_out;
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genvar i;
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generate
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for (i = 0; i < 4; i = i + 1) begin
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renderer r(.clk(clk), .rst(dir), .start(clk_div_8_counter[2:0] >> 1 == i), .x({x[i], 1'b0}), .y({y[i], 1'b0}), .done(), .iters(iters[i]));
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end
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endgenerate
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always_ff @(posedge clk) begin
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dir_last <= dir;
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req_last <= req;
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req_r <= !fin && !dir_last;
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if (dir) begin
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clk_div_8_counter <= 0;
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raddr <= 0;
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if (req && req_last) begin
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waddr <= waddr + 1;
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end else begin
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waddr <= 0;
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end
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end
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if (!dir && !dir_last) begin
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clk_div_8_counter <= clk_div_8_counter + 1;
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end
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end
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assign clk_div_8 = clk_div_8_counter[3];
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assign data_out = clk_div_8_counter[0] ? 128 : ((8'(iters[clk_div_8_counter[2:1]]) << 4) + 8'd62);
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assign req = dir ? 'Z : req_r;
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assign data = dir ? 'Z : data_out;
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endmodule |