75 lines
1.1 KiB
Systemverilog
75 lines
1.1 KiB
Systemverilog
module top
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(
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input wire clk,
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input wire dir,
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inout wire req,
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output wire fin,
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inout wire [7:0] data
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);
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reg dir_last;
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reg req_last;
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reg req_r;
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reg fin_r;
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reg [7:0] data_r;
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reg [6:0] x;
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reg [6:0] y;
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reg cntr;
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reg [7:0] waddr;
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reg [7:0] raddr;
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wire [7:0] command;
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RAM command_buffer(.wclk(clk), .rclk(clk), .waddr(waddr), .raddr(raddr), .data_in(data), .write_en(dir && req), .data_out(command));
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always_ff @(posedge clk) begin
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dir_last <= dir;
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req_last <= req;
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req_r <= !fin_r && !dir_last;
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if (dir) begin
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x <= 0;
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y <= 0;
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fin_r <= 0;
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cntr <= 0;
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raddr <= 0;
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if (req && req_last) begin
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waddr <= waddr + 1;
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end else begin
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waddr <= 0;
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end
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end else begin
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cntr <= !cntr;
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if (cntr) begin
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data_r <= command;
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raddr <= 1 - raddr;
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if (x + y == 0) begin
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fin_r <= 1;
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end
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end else begin
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data_r <= ((x + y) >> 1) + 16;
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if (x < 127) begin
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x <= x + 1;
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end else begin
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x <= 0;
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if (y < 127) begin
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y <= y + 1;
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end else begin
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y <= 0;
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end
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end
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end
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end
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end
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assign req = dir ? 'Z : req_r;
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assign fin = fin_r;
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assign data = dir ? 'Z : data_r;
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endmodule |