12 Commits

Author SHA1 Message Date
Stanislav Mekhanoshin
dd947ebcf3
[AMDGPU] Update gfx1250 memory model for global acquire/release (#175865)
Inserts required waits around GLOBAL_INV/GLOBAL_WBINV for
agent scope and above.
2026-01-15 03:25:03 -08:00
Pankaj Dwivedi
28d4e33b65
[AMDGPU][SIInsertWaitCnt] Optimize loadcnt insertion at function boundaries (#169647)
On GFX12+, GLOBAL_INV increments the loadcnt counter but does not write
results to any VGPRs. Previously, we unconditionally inserted
s_wait_loadcnt 0 at function returns even when the only pending loadcnt
was from GLOBAL_INV instructions.

This patch optimizes waitcnt insertion by skipping the loadcnt wait at
function boundaries when no VGPRs have pending loads. This is determined
by checking if any VGPR has a score greater than the lower bound for
LOAD_CNT - if not, the pending loadcnt must be from non-VGPR-writing
instructions like GLOBAL_INV.

The optimization is limited to GFX12+ targets where GLOBAL_INV exists
and uses the extended wait count instructions.

This is a follow-up optimization to PR #135340 which added tracking for
GLOBAL_INV in the waitcnt pass.
2025-12-17 17:53:00 +05:30
Christudasan Devadasan
a2dc4e02e7
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)
This patch enables the multi-group xnack replay mode by
configuring the hardware MODE register at kernel entry.
This aligns the hardware behavior with the compiler's
existing multi-group s_wait_xcnt insertion logic.
2025-11-21 19:42:17 +05:30
Brox Chen
3d4156700e
[AMDGPU][True16][CodeGen] lower flat_d16_saddr_t16 to saddr inst (#166603)
In true16 mode, D16 insts are lowered to a pseudo t16 first, and then
lowered to hi/lo inst in MC lowering using D16T16 table.

However, the D16T16 table selects both `flat_load_d16_t16 /
flat_load_d16_t16_saddr` to `flat_load_d16_(hi)_b16` which is wrong.
saddr pseudo inst `flat_load_d16_t16_saddr` should be selected to saddr
hi/lo inst

The global/scratch are correct while the flat seems to be the only one
with this issue.
2025-11-14 09:47:05 -05:00
Ryan Mitchell
5e4505d562
[AMDGPU][SIInsertWaitCnts] Gfx12.5 - Refactor xcnt optimization (#164357)
Refactor the XCnt optimization checks so that they can be checked when
applying a pre-existing waitcnt. This removes unnecessary xcnt waits
when taking a loop backedge.
2025-11-13 18:43:12 +00:00
Mirko Brkušanin
bdec5bf69c
[AMDGPU][GlobalISel] Combine (or s64, zext(s32)) (#151519)
If we only deal with a one part of 64bit value we can just generate
merge and unmerge which will be either combined away or
selected into copy / mov_b32.
2025-10-24 17:25:00 +02:00
Shilei Tian
e7f47e70e7
[AMDGPU] Enable XNACK on gfx1250 (#161457)
This should be always on.

Fixes SWDEV-555931.
2025-10-03 11:04:55 -04:00
Changpeng Fang
eb43b79765
[AMDGPU] Disable SGPR read hazard mitigation for gfx1250 (#150344)
Co-authored-by: Jay Foad <Jay.Foad@amd.com>
2025-07-24 00:05:58 -07:00
Stanislav Mekhanoshin
2346968807
[AMDGPU] Add V_ADD|SUB|MUL_U64 gfx1250 opcodes (#150291) 2025-07-23 13:17:56 -07:00
Stanislav Mekhanoshin
a0973de745
[AMDGPU] Select scale_offset for global instructions on gfx1250 (#150107)
Also switches immediate offset to signed for the subtarget.
2025-07-22 15:04:52 -07:00
Stanislav Mekhanoshin
c15a50ad22
[AMDGPU] More flatGVS gfx1250 patterns (#149410) 2025-07-17 16:10:59 -07:00
Stanislav Mekhanoshin
703501e661
[AMDGPU] Select flat GVS loads on gfx1250 (#149183) 2025-07-16 15:06:37 -07:00