530443 Commits

Author SHA1 Message Date
Helena Kotas
73e12de062
[HLSL] Implement explicit layout for default constant buffer ($Globals) (#128991)
Processes `HLSLResourceBindingAttr` attributes that represent
`register(c#)` annotations on default constant buffer declarations and
applies its value to the buffer layout. Any default buffer declarations
without an explicit `register(c#)` annotation are placed after the
elements with explicit layout.

This PR also adds a test case for a `cbuffer` that does not have
`packoffset` on all declarations. Same layout rules apply here as well.

Fixes #126791
2025-03-12 22:35:07 -07:00
Phoebe Wang
bc4b2c74fe
[X86][APX] Add NF instructions to convertToThreeAddress functions (#130969)
Since #130488, we have NF instructions when converting to three address
instructions.
2025-03-13 13:23:50 +08:00
Fangrui Song
642a4763df [PowerPC] Rename PPCMCExpr's VK_PPC_ to VK_. NFC
Make the name conciser. PPC-specific MCSymbolRefExpr::VariantKind
members will be moved to PPCMCExpr and we will not ue
MCSymbolRefExpr::VariantKind's "generic" members, so there won't be
mix-and-match.
2025-03-12 21:55:15 -07:00
Kuo, Mei-Chun
fe0d3e3764
[Sema] Diagnose by-value copy constructors in template instantiations (#130866)
Fixes #80963 

This PR ensures Clang diagnoses by-value copy constructors in implicitly
instantiated class templates (e.g., `A<int, int>(A<int, int>)`), per
[class.copy.ctor].

Changes: 
- Remove `TSK_ImplicitInstantiation` check in `SemaDeclCXX.cpp`.
- Add `!isFunctionTemplateSpecialization()` to skip templated
constructors.
- Add regression tests.
2025-03-13 05:52:42 +01:00
Fangrui Song
646a6e7f10 [PowerPC] Simplify PPCMCExpr::printImpl 2025-03-12 21:40:23 -07:00
Pengcheng Wang
08a3c53225
[RegAlloc] Scale the spill weight by target factor (#113675)
Currently, the spill weight is only determined by isDef/isUse and
block frequency. However, for registers with different register
classes, the costs of spilling them are different.

For example, for `LMUL>1` registers (in which, several physical
registers compound a bigger logical register), the costs are larger
than `LMUL=1` case (in which, there is only one physical register).

To solve this problem, a new target hook `getSpillWeightScaleFactor`
is added. Targets can override the default factor (which is `1.0`)
according to the register class.

For RISC-V, the factors are set to the `RegClassWeight` which is
used to track register pressure. The values of `RegClassWeight`
happen to be the number of register units.

I believe all of the targets with compounded registers can benefit
from this change, but only RISC-V is customized in this patch since
it has widely been agreed to do so. The other targets need more
performance data to go further.

Partially fixes #113489.
2025-03-13 12:27:59 +08:00
Christopher Bate
3438dfc7ff
[mlir][tensor] Fix bufferization interface for 'tensor.reshape' (#128590)
Previously, the BufferizableOpInterface implementation for
'tensor.reshape'
listed the 'shape' operand as an alias for the result tensor, causing
unnecessary conflicts with ops that "write" to the shape operand.
2025-03-12 22:19:01 -06:00
Pengcheng Wang
376e3b62cd
[TableGen] Add !match operator to do regex matching (#130759)
The grammar is `!match(str, regex)` and this operator produces 1
if the `str` matches the regular expression `regex`.

The format of `regex` is ERE (Extended POSIX Regular Expressions).
2025-03-13 12:13:09 +08:00
Connector Switch
f291ec692e
[libc] Use proxy header in the locale implementation. (#130982)
Address review comments in
https://github.com/llvm/llvm-project/pull/130621#pullrequestreview-2671843932.

Some unused headers are also removed.
2025-03-13 11:35:41 +08:00
LLVM GN Syncbot
79a5974294 [gn build] Port 4dcba5e08dc9 2025-03-13 03:21:36 +00:00
Ryosuke Niwa
4dcba5e08d
[alpha.webkit.ForwardDeclChecker] Add a new WebKit checker for forward declarations (#130554)
Add a new static analyzer which emits warnings for function call
arguments, local variables, and member variables that are only forward
declared. These forward declaration prevents other WebKit checkers from
checking the safety of code.
2025-03-12 20:21:22 -07:00
Craig Topper
62e37a8a0a
[RISCV][Disassembler] Use a table to store all the decoder tables and their associated features. NFC (#130883)
Replace the macros with a table that we can iterate over. Use a
different table for each possible instruction bitwidth.
2025-03-12 20:15:17 -07:00
Lang Hames
853849a984 [ORC] Remove some unnecessary namespace qualifications. NFCI. 2025-03-13 14:15:01 +11:00
Matt Arsenault
0a78bd67b3
AMDGPU: Make frexp_exp and frexp_mant intrinsics propagate poison (#130915) 2025-03-13 10:07:45 +07:00
Chuanqi Xu
4d8070e956 [C++20] [Modules] Don't add decls from other units to undefinedButUsed set
It is still better to elide the declaration if possible. To overcome the
false positive undefinedButUsed diagnostic, it seems better to not add
declaration from other units to the set actually.
2025-03-13 11:02:57 +08:00
Matt Arsenault
d8f17b3de1
AMDGPU: Make sqrt and rsq intrinsics propagate poison (#130914) 2025-03-13 10:01:48 +07:00
Matt Arsenault
95ab95fd10
AMDGPU: Make rcp intrinsic propagate poison (#130913) 2025-03-13 09:58:46 +07:00
Fangrui Song
eea7d32bd2 [MC] Move fixSymbolsInTLSFixups to ELFObjectWriter
so that we only need to do it once during recordRelocation. In the
future, we should change fixSymbolsInTLSFixups to apply to MCValue
instead of MCExpr, similar to GNU assembler.
2025-03-12 19:49:52 -07:00
LLVM GN Syncbot
e4a0fd5416 [gn build] Port be9ca85d64eb 2025-03-13 02:09:36 +00:00
Ryosuke Niwa
be9ca85d64
[alpha.webkit.webkit.RetainPtrCtorAdoptChecker] Add a new WebKit checker for correct use of RetainPtr, adoptNS, and adoptCF (#128679)
Add a new WebKit checker to validate the correct use of RetainPtr
constructor as well as adoptNS and adoptCF functions. adoptNS and
adoptCf are used for +1 semantics and RetainPtr constructor is used for
+0 semantics.
2025-03-12 19:09:05 -07:00
Matt Arsenault
12fe5ae88c
AMDGPU: Replace ptr addrspace(8) undef uses with poison (#130904) 2025-03-13 08:37:51 +07:00
Ryosuke Niwa
27d83184c4
[alpha.webkit.UncountedCallArgsChecker] Treat an explicit construction of Ref from a Ref return value safe. (#130911)
Fix a bug that an explicit construction of Ref out of a Ref return value
would not be treated as safe. It is definitely safe albit redundant.
2025-03-12 18:33:17 -07:00
Matt Arsenault
e1e44dfcad
AMDGPU: Replace <8 x i32> undef uses in tests with poison (#130903) 2025-03-13 08:31:57 +07:00
Matt Arsenault
c182f4042a
AMDGPU: Replace <4 x i32> undef uses in tests with poison (#130902)
Most of these are from resource descriptors.
2025-03-13 08:28:48 +07:00
Matt Arsenault
6705d812b8
AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)
Many tests use store to undef as a placeholder use, so just replace
all of these with poison.
2025-03-13 08:25:02 +07:00
Jonas Hahnfeld
44ff94e99e
[Diagnostics] Return rvalue reference from temporary argument (#127400)
This fixes compilation issues with GCC and C++23:
```
error: cannot bind non-const lvalue reference of type
'llvm::OptimizationRemarkMissed&' to an rvalue of type
'llvm::OptimizationRemarkMissed'
```

Closes #105778
2025-03-13 08:07:07 +07:00
Brox Chen
cb73271be1
[AMDGPU][CodeGen] use vt in VGPRimm pattern (#131016)
There seems to be a typo error introduced by
2033767d68

Correct this pattern to use vt.
2025-03-13 07:58:19 +07:00
Krzysztof Parzyszek
f4fc2d731c
[flang][OpenMP] Map ByRef if size/alignment exceed that of a pointer (#130832)
Improve the check for whether a type can be passed by copy. Currently,
passing by copy is done via the OMP_MAP_LITERAL mapping, which can only
transfer as much data as can be contained in a pointer representation.
2025-03-12 19:41:11 -05:00
Slava Zakharin
c542991703
[flang-rt] Fixed HAVE_LDBL_MANT_DIG_113 detection. (#131010)
I thought I guessed a fix in #130836, but I was wrong.
We actually had the same code in
`flang/cmake/modules/FlangCommon.cmake`.
The check does not pass in flang-rt bootstrap build, because
`-nostdinc++` is added for all `runtimes` checks.
I decided to make the check with the C header, though, I am still
unsure whether it is reliable with a clang that has not been
installed (it is taken from the build structure during flang-rt
configure step).
I verified that this PR enables REAL(16) math entries on aarch64.
2025-03-12 16:50:01 -07:00
Artem Pianykh
726ffd361c
[NFC][Cloning] Replace IdentityMD set with a predicate in ValueMapper (#129147)
Summary:
We used the set only to check if it contains certain metadata nodes.
Replacing the set with a predicate makes the intention clearer and the
API more general.

Test Plan:
ninja check-all
2025-03-12 23:33:12 +00:00
Adrian Prantl
98c279a3ed [lldb] Add missing optional conversion 2025-03-12 16:21:59 -07:00
Arthur Eubanks
1cfca53b9f
[llvm][Timer] Don't print timers in TimerGroup when all Timers are removed (#131026)
Only print them on TimerGroup destruction (or eagerly when
TimerGroup::printAll() is called).

We should be able to destroy all Timers in a TimerGroup while delaying
printing the stored TimeRecords.
2025-03-12 16:20:13 -07:00
Oleksandr T.
c14e459ef8
[Clang] add additional tests for -Wshift-bool (#130339)
Fixes
https://github.com/llvm/llvm-project/pull/127336#pullrequestreview-2665950553
2025-03-13 01:10:40 +02:00
Javed Absar
ecf4d995f6
[mlir][linalg][elementwise] Fold transpose into new elementwise (#130207)
Fold transpose into new elementwise Op which has affine-map attached.
Will add broadcast folding in next diff.
2025-03-12 23:04:44 +00:00
Andy Kaylor
be0215d745
[CIR] Add transform test for cir-flatten-cfg (#130861)
A previous change added the cir-flatten-cfg transform and tested it by
lowering a function with nested scopes to LLVM IR. This change adds
support for invoking the cir-flatten-cfg pass from the cir-opt tool and
adds a new test to verify that functionality in isolation.
2025-03-12 15:13:31 -07:00
Florian Hahn
62994c3291
[VPlan] Also introduce explicit broadcasts for values from entry VPBB.
Update and generalize materializeBroadcasts to also introduce explicit
broadcasts for VPValues defined in the Plans Entry block.

This fixes a crash when trying to insert the broadcasts generated by
VPTransformState::get after the generating instruction, which isn't
possible after invoke instructions.

Fixes https://github.com/llvm/llvm-project/issues/128838.
2025-03-12 22:03:19 +00:00
Abinaya Saravanan
9c65e6ac11
[HEXAGON] Add support to lower "FREEZE a half(f16)" instruction on Hexagon and fix the isel-buildvector-v2f16.ll assertion (#130977) 2025-03-12 16:58:26 -05:00
Alexey Bataev
202137dbea [SLP]Fix a crash on matching gather operands of phi nodes in loops
If the gather operands in phi nodes are matching and phi nodes may build
up a loop, it may cause a compiler crash with the incorrect def-use
chain. Patch fixes this crash.
2025-03-12 14:46:00 -07:00
Andy Kaylor
64b94105d5
[CIR] Upstream support for emitting ignored statements (#130869)
This adds support for emitting ClangIR for statements whose value is
ignored. The test case being added (CIR/CodeGen/basic.c) tests a few
more things. The "f1" test case is the only part that's immediately
relevant to this change, but the other cases were part of the same test
in the incubator and they are supported so I brought in the entire test.
2025-03-12 14:38:19 -07:00
Jon Chesterfield
cba9dc6e9d
[libc][nfc] Use common implementation of read_first_lane_u64 (#131027)
No codegen regression on either target. The two builtin_ffs implied on
nvptx CSE away.

```
define internal i64 @__gpu_read_first_lane_u64(i64 noundef %__lane_mask, i64 noundef %__x) #2 {
entry:
  %shr = lshr i64 %__x, 32
  %conv = trunc nuw i64 %shr to i32
  %conv1 = trunc i64 %__x to i32
  %conv2 = trunc i64 %__lane_mask to i32
  %0 = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 %conv2, i1 true)
  %iszero = icmp eq i32 %conv2, 0
  %sub = select i1 %iszero, i32 -1, i32 %0
  %1 = tail call i32 @llvm.nvvm.shfl.sync.idx.i32(i32 %conv2, i32 %conv, i32 %sub, i32 31)
  %conv4 = sext i32 %1 to i64
  %shl = shl nsw i64 %conv4, 32
  %2 = tail call i32 @llvm.nvvm.shfl.sync.idx.i32(i32 %conv2, i32 %conv1, i32 %sub, i32 31)
  %conv7 = zext i32 %2 to i64
  %or = or disjoint i64 %shl, %conv7
  ret i64 %or
}
; becomes

define internal i64 @__gpu_competing_read_first_lane_u64(i64 noundef %__lane_mask, i64 noundef %__x) #2 {
entry:
  %shr = lshr i64 %__x, 32
  %conv = trunc nuw i64 %shr to i32
  %conv1 = trunc i64 %__x to i32
  %conv.i = trunc i64 %__lane_mask to i32
  %0 = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 %conv.i, i1 true)
  %iszero = icmp eq i32 %conv.i, 0
  %sub.i = select i1 %iszero, i32 -1, i32 %0
  %1 = tail call i32 @llvm.nvvm.shfl.sync.idx.i32(i32 %conv.i, i32 %conv, i32 %sub.i, i32 31)
  %conv4 = zext i32 %1 to i64
  %shl = shl nuw i64 %conv4, 32
  %2 = tail call i32 @llvm.nvvm.shfl.sync.idx.i32(i32 %conv.i, i32 %conv1, i32 %sub.i, i32 31)
  %conv7 = zext i32 %2 to i64
  %or = or disjoint i64 %shl, %conv7
  ret i64 %or
}
```

The sext vs zext difference is vaguely interesting but since the bits
are immediately discarded in either case it make no odds. The amdgcn one
doesn't need CSE, the readfirstlane function is a single call to an
intrinsic.

Drive by fix to __gpu_match_all_u32, it was calling first_lane_u64 and
could use first_lane_u32 instead. Added the missing call to gpuintrin.c
test case and a stray missing static as well.
2025-03-12 21:29:46 +00:00
Shilei Tian
c476a4a907
[Clang][OpenCL] Fix Missing -fdeclare-opencl-builtins When Using --save-temps (#131017)
When compiling an OpenCL program directly with `clang` using
`--save-temps`, an
error may occur if the program contains OpenCL builtins:

```
test.cl:3:21: error: use of undeclared identifier 'get_global_id'
    3 |   unsigned int id = get_global_id(0);
      |                     ^
```

This happens because the driver does not add `-fdeclare-opencl-builtins`
when
the input type is `TY_PP_CL`. This PR fixes the issue.
2025-03-12 17:00:19 -04:00
Brox Chen
c8047c6dbc
[AMDGPU][True16][CodeGen] update test for buildbot failure (#131028)
This is a NFC patch

https://github.com/llvm/llvm-project/pull/103366 hit a buildbot failure
with i1-to-bf16.ll. Update the test to fix the build.

Also remove duplicated comments added in
https://github.com/llvm/llvm-project/pull/103366
2025-03-12 16:59:48 -04:00
Lang Hames
15e6bb6224 [ORC] Rename wrapper arguments to match conventions. NFCI. 2025-03-13 07:36:17 +11:00
Brox Chen
9d7e1d92db
[AMDGPU][True16] added Pre-RA hint to improve copy elimination (#103366)
The allocation order of 16 bit registers is vgpr0lo16, vgpr0hi16,
vgpr1lo16, vgpr1hi16, vgpr2lo16.... We prefer (essentially require) that
allocation order, because it uses the minimum number of registers. But
when you have 16 bit data passing between 16 and 32 bit instructions you
get lots of COPY.

This patch teach the compiler that a COPY of a 16-bit value from a 32
bit register to a lo-half 16 bit register is free, to a hi-half 16 bit
register is not.

This might get improved to coalescing with additional cases, and perhaps
as an alternative to the RA hints. For now upstreaming this solution
first.
2025-03-12 16:12:58 -04:00
LLVM GN Syncbot
5929de8c77 [gn build] Port 7790d69cce04 2025-03-12 19:29:18 +00:00
John Harrison
7790d69cce
[lldb-dap] Refactoring IOStream into Transport handler. (#130026)
Instead of having two discrete InputStream and OutputStream helpers,
this merges the two into a unifed 'Transport' handler.

This handler is responsible for reading the DAP message headers, parsing
the resulting JSON and converting the messages into
`lldb_dap::protocol::Message`s for both input and output.

---------

Co-authored-by: Jonas Devlieghere <jonas@devlieghere.com>
2025-03-12 12:29:05 -07:00
Kazu Hirata
4d79e9892c
[Support] Avoid repeated hash lookups (NFC) (#130891)
Co-authored-by: Nikita Popov <github@npopov.com>
2025-03-12 12:19:53 -07:00
Kazu Hirata
aa008e0008 Revert "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)"
This reverts commit 71582c6667a6334c688734cae628e906b3c1ac1d.

Multiple buildbot failures have been reported:
https://github.com/llvm/llvm-project/pull/127212
2025-03-12 12:09:09 -07:00
Joseph Huber
598e882ee8
[libc] Template the writing mode for the writer class (#111559)
Summary:
Currently we dispatch the writing mode off of a runtime enum passed in
by the constructor. This causes very unfortunate codegen for the GPU
targets where we get worst-case codegen because of the unused function
pointer for `sprintf`. Instead, this patch moves all of this to a
template so it can be masked out. This results in no dynamic stack and
uses 60 VGPRs instead of 117. It also compiles about 5x as fast.
2025-03-12 13:51:44 -05:00
Rémy Neveu
3aa96f52cf
[OpenMP] [Taskgraph] Differentiating task ids from the taskgraph and from the debugger (#130660)
This PR creates a new member for task data, which is used to identify
the task in its taskgraph (when ompx taskgraph is enabled).
It aims to remove the overloading of the td_task_id member, which was
used both by the debugger and the taskgraph. This resulted in the
identifier's non-unicity in the case of multiple taskgraphs.

Co-authored-by: Rémy Neveu <rem2007@free.fr>
2025-03-12 11:39:02 -07:00