611 Commits

Author SHA1 Message Date
pvanhout
844c0da777 [TableGen][GlobalISel] Add MIR Pattern Builtins
Adds a new feature to MIR patterns: builtin instructions.
They offer some additional capabilities that currently cannot be expressed without falling back to C++ code.
There are two builtins added with this patch, but more can be added later as new needs arise:
 - GIReplaceReg
 - GIEraseRoot

Depends on D158714, D158713

Reviewed By: arsenm, aemerson

Differential Revision: https://reviews.llvm.org/D158975
2023-09-05 08:19:07 +02:00
pvanhout
4e513f69a1 [GlobalISel] Cleanup Combine.td
Now that the old backend is gone, clean-up a few things that no longer make sense and tidy up the file a bit.

Depends on D158710

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D158714
2023-09-05 08:19:06 +02:00
Matt Arsenault
ad9d13d535 SelectionDAG: Swap operands of atomic_store
Irritatingly, atomic_store had operands in the opposite order from
regular store. This made it difficult to share patterns between
regular and atomic stores.

There was a previous incomplete attempt to move atomic_store into the
regular StoreSDNode which would be better.

I think it was a mistake for all atomicrmw to swap the operand order,
so maybe it's better to take this one step further.

https://reviews.llvm.org/D123143
2023-08-31 17:30:10 -04:00
pvanhout
54d0cf58fb [TableGen] Remove & Replace old GICombiner Backend
The MatchTable-based GlobalISel Combiner backend is the new default. There are no in-tree users left of the old backend.

- Removed implementation of old MatchDAG-based Combiner, including tests, the backend itself and all supporting code.
- Renamed MatchTable backend to `GlobalISelCombinerEmitter.cpp` + removed "-matchtable" from its CL option.
    - no need to have a verbose name as it's the only backend left now.

Reviewed By: aemerson

Differential Revision: https://reviews.llvm.org/D158710
2023-08-31 13:16:07 +02:00
Michael Maitland
85e3875ad7 [TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics
D150312 added a TODO:

TODO: consider renaming the field `StartAtCycle` and `Cycles` to
`AcquireAtCycle` and `ReleaseAtCycle` respectively, to stress the
fact that resource allocation is now represented as an interval,
relatively to the issue cycle of the instruction.

This patch implements that TODO. This naming clarifies how to use these
fields in the scheduler. In addition it was confusing that `StartAtCycle` was
singular but `Cycles` was plural. This renaming fixes this inconsistency.

This commit as previously reverted since it missed renaming that came
down after rebasing. This version of the commit fixes those problems.

Differential Revision: https://reviews.llvm.org/D158568
2023-08-24 19:21:36 -07:00
Michael Maitland
71bfec762b Revert "[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics"
This reverts commit 5b854f2c23ea1b000cb4cac4c0fea77326c03d43.

Build still failing.
2023-08-24 15:37:27 -07:00
Michael Maitland
5b854f2c23 [TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics
D150312 added a TODO:

TODO: consider renaming the field `StartAtCycle` and `Cycles` to
`AcquireAtCycle` and `ReleaseAtCycle` respectively, to stress the
fact that resource allocation is now represented as an interval,
relatively to the issue cycle of the instruction.

This patch implements that TODO. This naming clarifies how to use these
fields in the scheduler. In addition it was confusing that `StartAtCycle` was
singular but `Cycles` was plural. This renaming fixes this inconsistency.

This commit as previously reverted since it missed renaming that came
down after rebasing. This version of the commit fixes those problems.

Differential Revision: https://reviews.llvm.org/D158568
2023-08-24 15:25:42 -07:00
Michael Maitland
4d27dffb43 Revert "[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics"
This reverts commit 030d33409568b2f0ea61116e83fd40ca27ba33ac.

This commit is causing build failures
2023-08-24 11:58:53 -07:00
Michael Maitland
030d334095 [TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics
D150312 added a TODO:

TODO: consider renaming the field `StartAtCycle` and `Cycles` to
`AcquireAtCycle` and `ReleaseAtCycle` respectively, to stress the
fact that resource allocation is now represented as an interval,
relatively to the issue cycle of the instruction.

This patch implements that TODO. This naming clarifies how to use these
fields in the scheduler. In addition it was confusing that `StartAtCycle` was
singular but `Cycles` was plural. This renaming fixes this inconsistency.

Differential Revision: https://reviews.llvm.org/D158568
2023-08-24 11:20:37 -07:00
pvanhout
0a59e1a85c [GlobalIsSel] Allow using PatFrags with multiple defs as the root of a combine rule
I had to tighten the restrictions on PatFrags a bit to make it consistent: instructions that
define the root of a PF can only have one def.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D157700
2023-08-24 09:09:24 +02:00
Craig Topper
e1a0e8258f [GlobalISel] Copy the implementation of SubtargetFeature and use it for PredicateBitset.
PredicateBitset currently uses std::bitset, but std::bitset doesn't
have a constexpr constructor or any constexpr methods until C++23.
Each target that supports GlobalIsel has as an array of PredicateBitset
objects that currently use a global constructor.

SubtargetFeature used by the MC layer for feature bits, has its own
implementation of std::bitset that has constexpr constructor and methods
that provides all the capabilities that PredicateBitset needs.

This patch copies the implementation from SubtargetFeature, makes
it a template class, and puts it in ADT. I'll migrate SubtargetFeature
in a separate patch. Adapting all existing users to it being a template
was distracting from the goal of this patch.

This reduces the binary size of llc built with gcc 8.5.0 on my local
build by ~15k.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D158576
2023-08-23 15:55:44 -07:00
Senran Zhang
cd7280b6e6 [TableGen] Fix wrong lex result on 64-bit integer boundaries
Binary and decimal values were reconginzed by strtoll, which returns
error when the msb is 1, and the error was ignored, resulting to wrong
results.

This patch fixes the issue.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D157079
2023-08-20 21:46:36 -07:00
pvanhout
63afb70503 [RFC][GlobalISel] Overhauled MIR Patterns Support for Combiners
See https://discourse.llvm.org/t/rfc-overhauled-mir-patterns-for-globalisel-combiners/72264

This is a complete overrhaul of the recently-added GlobalISel Match Table backend which adds
support for MIR patterns for both match and apply patterns.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D156315
2023-08-11 08:54:56 +02:00
wangpc
eb6987027e [TableGen] Improve error report of unspecified arguments
Wrong error message is fixed and a note of argument is printed.

Tests are added in `llvm/test/TableGen/template-args.td`.

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D156966
2023-08-03 17:22:34 +08:00
Ivan Kosarev
5775db2e7b [TableGen][RegisterInfoEmitter] Make entries of base register class tables human-readable.
Helps tracking changes in the tables on adding new register classes and
updating BaseClassOrder values.

Also eliminates tables translating base register class indexes into
TargetRegisterClass pointers.

Reviewed By: critson

Differential Revision: https://reviews.llvm.org/D156097
2023-07-27 10:42:21 +01:00
pvanhout
2f1244cfda [test][TableGen] Reenable pattern-parsing.td with reverse_iteration
D155821 should have fixed this.
2023-07-24 12:22:26 +02:00
pvanhout
d7c6d057ef [TableGen][GlobalISel] Guarantee stable iteration order for stop-after-parse
Builds on top of 6de2735c2428 to fix remaining issues with iteration order in the MatchTable Combiner backend.
See D155789 as well.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D155821
2023-07-24 09:10:50 +02:00
Fangrui Song
9996e71f2d [Support] Implement LLVM_ENABLE_REVERSE_ITERATION for StringMap
ProgrammersManual.html says

> StringMap iteration order, however, is not guaranteed to be deterministic, so any uses which require that should instead use a std::map.

This patch makes -DLLVM_REVERSE_ITERATION=on (currently
-DLLVM_ENABLE_REVERSE_ITERATION=on works as well) shuffle StringMap
iteration order (actually flipping the hash so that elements not in the
same bucket are reversed) to catch violations, similar to D35043 for
DenseMap. This should help change the hash function (e.g., D142862,
D155781).

With a lot of fixes, there are still some violations. This patch
implements the "reverse_iteration" lit feature to skip such tests.
Eventually we should remove this feature.

`ninja check-{llvm,clang,clang-tools}` are clean with
`#define LLVM_ENABLE_REVERSE_ITERATION 1`.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D155789
2023-07-21 08:46:51 -07:00
wangpc
91ccbc6c1c [TableGen] Support named arguments
We provide a way to specify arguments in the form of `name=value`
so that we don't have to specify all optional arguments before the
one we'd like to change. Required arguments can alse be specified
in this way.

Note that the argument can only be specified once regardless of
the way (named or positional) to specify and positional arguments
should be put before named arguments.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D152998
2023-07-20 16:03:17 +08:00
Freddy Ye
1c154bd755 [X86] Add AVX-VNNI-INT16 instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D155145
2023-07-20 14:31:16 +08:00
Freddy Ye
049d6a3f42 [X86] Add SM4 instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D155148
2023-07-20 13:35:15 +08:00
Freddy Ye
c6f66de21a [X86] Add SM3 instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D155147
2023-07-20 10:24:16 +08:00
Nikita Popov
8ecc6c9378 [IR] Partially remove pointer element types from intrinsic signatures (NFC)
As typed pointers are no longer supported, we should no longer
specify element types in intrinsic signatures.

The only meaningful pointer types are now:

    llvm_ptr_ty -> ptr
    llvm_anyptr_ty -> ptr addrspace(any)
    LLVMQualPointerType<N> -> ptr addrspace(N)

This is only "partially" because we also have a bunch of special
IIT descriptors like LLVMPointerTo, LLVMPointerToElt and
LLVMAnyPointerToElt, which I'll leave for a later revision.

Differential Revision: https://reviews.llvm.org/D155086
2023-07-13 10:00:51 +02:00
pvanhout
c0719f3bac [RFC][TableGen][GlobalISel] Add Combiner Match Table Backend
Adds a new backend to power the GISel Combiners using the InstructionSelector's match tables.
This does not depend on any of the data structures created for the current combiner and is intended to replace it entirely.

See the RFC for more details: https://discourse.llvm.org/t/rfc-matchtable-based-globalisel-combiners/71457/6
Note: this would replace D141135.

Reviewed By: aemerson, arsenm

Differential Revision: https://reviews.llvm.org/D153757
2023-07-11 09:42:39 +02:00
pvanhout
908d0d54b8 [TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter
Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well.

Depends on D153755

Reviewed By: aemerson

Differential Revision: https://reviews.llvm.org/D153756
2023-07-11 09:42:35 +02:00
pvanhout
1fe7d9c799 [GlobalISel] Generalize InstructionSelector Match Tables
Makes `InstructionSelector.h`/`InstructionSelectorImpl.h` generic so the match tables can also be used for the combiner.

Some notes:
 - Coverage was made an optional parameter of `executeMatchTable`, combines won't use it for now.
 - `GIPFP_` -> `GICXXPred_` so it's more generic. Those are just C++ predicates and aren't PatFrag-specific.
 - Pass the MatcherState directly to testMIPredicate_MI, the combiner will need it.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D153755
2023-07-11 09:42:30 +02:00
Valentin Clement
ed7337506e
[tblgen][directive] Fix clause parser generation for list value
The clause parser generation was not taking into account the
`isValueList` flag. This patch updates the emitter to generate
the correct code.

Reviewed By: razvanlupusoru

Differential Revision: https://reviews.llvm.org/D153801
2023-06-27 11:09:23 -07:00
Matt Arsenault
1717c18664 Intrinsics: Allow tablegen to mark parameters with dereferenceable 2023-06-21 21:36:22 -04:00
Michael Liao
dcc8f9490f [TableGen] Add !setdagarg and !setdagname
- This patch proposes to add `!setdagarg` and `!setdagname` bang
  operators to produce a new DAG node after replacing the specified
  argument value/name from the given input DAG node. E.g.,
  `!setdagarg((foo 1, 2), 0, "x")` produces `(foo "x", 2)` and
  `!setdagname((foo 1:$a, 2:$b), 1, "c")` produces `(foo 1:$a, 2:$c)`.

Reviewed By: simon_tatham

Differential Revision: https://reviews.llvm.org/D151842
2023-06-07 09:37:40 -04:00
Stanislav Mekhanoshin
a15eb89aba [TableGen] Allow bit fields in SearchableTables.
Differential Revision: https://reviews.llvm.org/D151756
2023-06-02 13:49:07 -07:00
Michael Liao
26d7b7bb8f [TableGen] Add !getdagarg and !getdagname
- This patch proposes to add `!getdagarg` and `!getdagname` bang
  operators as the inverse operation of `!dag`. They allow us to examine
  arguments of a given dag.

Reviewed By: simon_tatham

Differential Revision: https://reviews.llvm.org/D151602
2023-05-31 10:54:43 -04:00
wangpc
45ea4d6256 [TableGen] Unify the priority of variables
In D148197, we have made `defvar` statement able to refer to class
template arguments. However, the priority of class/multiclass
template argument is higher than variables defined by `defvar`, which
is a little counterintuitive.

In this patch, we unify the priority of variables. Each pair of
braces introduces a new scope, which may contain some additional
variables like template arguments, loop iterators, etc. We can
define local variables inside this scope via `defvar` and these
variables are of higher priority than additional variables. This
means that `defvar` will shadow additional variables with the same
name. The scope can be nested, and we use the innermost variable.

This make variables defined by `defvar` prior to class/multiclass
template arguments, loop iterators, etc. The shadow rules now are:

* `V` in a record body shadows a global `V`.

* `V` in a record body shadows template argument `V`.

* `V` in template arguments shadows a global `V`.

* `V` in a `foreach` statement list shadows any `V` in surrounding record or global scopes.

Reviewed By: tra

Differential Revision: https://reviews.llvm.org/D149016
2023-05-24 12:44:14 +08:00
Shengchen Kan
c81a121f3f Revert "Revert "[X86] Remove patterns for ADC/SBB with immediate 8 and optimize during MC lowering, NFCI""
This reverts commit cb16b33a03aff70b2499c3452f2f817f3f92d20d.

In fact, the test https://bugs.chromium.org/p/chromium/issues/detail?id=1446973#c2
already passed after 5586bc539acb26cb94e461438de01a5080513401
2023-05-19 22:21:56 +08:00
Hans Wennborg
cb16b33a03 Revert "[X86] Remove patterns for ADC/SBB with immediate 8 and optimize during MC lowering, NFCI"
This caused compiler assertions, see comment on
https://reviews.llvm.org/D150107.

This also reverts the dependent follow-up change:

> [X86] Remove patterns for ADD/AND/OR/SUB/XOR/CMP with immediate 8 and optimize during MC lowering, NFCI
>
> This is follow-up of D150107.
>
> In addition, the function `X86::optimizeToFixedRegisterOrShortImmediateForm` can be
> shared with project bolt and eliminates the code in X86InstrRelaxTables.cpp.
>
> Differential Revision: https://reviews.llvm.org/D150949

This reverts commit 2ef8ae134828876ab3ebda4a81bb2df7b095d030 and
5586bc539acb26cb94e461438de01a5080513401.
2023-05-19 14:43:33 +02:00
Shengchen Kan
5586bc539a [X86] Remove patterns for ADD/AND/OR/SUB/XOR/CMP with immediate 8 and optimize during MC lowering, NFCI
This is follow-up of D150107.

In addition, the function `X86::optimizeToFixedRegisterOrShortImmediateForm` can be
shared with project bolt and eliminates the code in X86InstrRelaxTables.cpp.

Differential Revision: https://reviews.llvm.org/D150949
2023-05-19 18:22:30 +08:00
Tobias Hieta
f84bac329b
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
This is a follow-up to b71edfaa4ec3c998aadb35255ce2f60bba2940b0
since I forgot the lit.local.cfg files in that one.

Reformatting is done with `black`.

If you end up having problems merging this commit because you
have made changes to a python file, the best way to handle that
is to run git checkout --ours <yourfile> and then reformat it
with black.

If you run into any problems, post to discourse about it and
we will try to help.

RFC Thread below:

https://discourse.llvm.org/t/rfc-document-and-standardize-python-code-style

Reviewed By: barannikov88, kwk

Differential Revision: https://reviews.llvm.org/D150762
2023-05-17 17:03:15 +02:00
Tobias Hieta
b71edfaa4e
[NFC][Py Reformat] Reformat python files in llvm
This is the first commit in a series that will reformat
all the python files in the LLVM repository.

Reformatting is done with `black`.

See more information here:

https://discourse.llvm.org/t/rfc-document-and-standardize-python-code-style

Reviewed By: jhenderson, JDevlieghere, MatzeB

Differential Revision: https://reviews.llvm.org/D150545
2023-05-17 10:48:52 +02:00
Francesco Petrogalli
4bfe410802 [TableGen][SubtargetEmitter] Add the StartAtCycles field in the WriteRes class.
Conditions that need to be met:

1. count(StartAtCycle) == count(ReservedCycles);
2. For each i: StartAtCycles[i] < ReservedCycles[i];
3. For each i: StartAtCycles[i] >= 0;
4. If left unspecified, the elements are set to 0.

Differential Revision: https://reviews.llvm.org/D150310
2023-05-15 10:39:45 +02:00
NAKAMURA Takumi
f98192af55 TableGen: Let expressions available to list subscriptions and list slices
This enables indexing in `!foreach` and permutation with `list[permlist]`.

Enhancements in syntax:

  - `list<int>` is applicable as a slice element.
  - `list[int,]` is evaluated as not `ElemType` but `list<ElemType>`
    with a single element.

Part of D145872

FIXME: I didn't apply new semantics to BitSlice.
2023-04-26 23:47:16 +09:00
NAKAMURA Takumi
f8ee342f44 Add failure testcases as llvm/test/TableGen/ListSlices-fail.td
Differential Revision: https://reviews.llvm.org/D147401
2023-04-26 23:47:15 +09:00
NAKAMURA Takumi
ab2187d786 TableGen: Introduce !range operator for half-opened interval
`!range(a, b)` generates a list `[a,b)`. `a` is optional and `0` by default.

  - `!range(-1, 4)` generates `[-1, 0, 1, 2, 3]`
  - `!range(4)` generates `[0, 1, 2, 3]`
  - `!range(2, 2)` generates `[]<list<int>>`

`!range(list)` is equivalent to `!range(0, !size(list))`.

Differential Revision: https://reviews.llvm.org/D145871
2023-04-25 22:38:20 +09:00
Chen Zheng
3f4055dec4 [GlobalISelEmitter] handle operand without MVT/class
There are some patterns in td files without MVT/class set
for some operands in target pattern that are from the source
pattern. This prevents GlobalISelEmitter from adding them as
a valid rule, because the target child operand is an
unsupported kind operand. For now, for a leaf child, only
IntInit and DefInit are handled in GlobalISelEmitter.

This issue can be workaround by adding MVT/class to the
patterns in the td files, like the workarounds for patterns
anyext and setcc in PPCInstrInfo.td in D140878.

To avoid adding the same workarounds for other patterns in
td files, this patch tries to handle the UnsetInit case in
GlobalISelEmitter.

Adding the new handling allows us to remove the workarounds
in the td files and also generates many selection rules for
PPC target.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D141247
2023-04-19 07:00:57 +00:00
wangpc
fd5d0a88dd [TableGen] Allow references to class template arguments in defvar
We can't refer to template arguments for defvar statements in class
definitions, or it will report some errors like:

```
error: Variable not defined: 'xxx'.
```

The key point here is we used to pass nullptr to `ParseValue` in
`ParseDefvar`. As a result, we can't refer to template arguments
since `CurRec` is nullptr in `ParseIDValue`.

So we add an argument `CurRec` to `ParseDefvar` and provide it
when parsing defvar statements in class definitions.

Reviewed By: tra, simon_tatham

Differential Revision: https://reviews.llvm.org/D148197
2023-04-14 11:12:35 +08:00
Nico Weber
cbe4499d6b Revert "[X86][mem-fold] Speed up test by not re-generating the .inc file"
This reverts commit 070233dab0fdc6098a8b645774003fb0511e5962.

It also reverts follow-ups 2588e831af4a2240825215670c53717f07a95b3a and
027f60a6e9fa0b2ddf9eecc65aab8fde0b527f51.
2023-04-11 08:17:55 -04:00
Shengchen Kan
027f60a6e9 [X86][mem-fold] Use x86-registered-target in the tablgen test, NFCI 2023-04-11 14:07:20 +08:00
Shengchen Kan
2588e831af [X86][mem-fold] Only run x86-fold-tables.test when target x86 is built
Avoid the LIT fail when only arm/aarch64 is built.
2023-04-11 12:48:44 +08:00
Shengchen Kan
070233dab0 [X86][mem-fold] Speed up test by not re-generating the .inc file
Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D147835
2023-04-11 12:05:13 +08:00
Chen Zheng
bc257ff07b [GlobalISelEmitter] add case for D141247, NFC. 2023-04-10 01:11:26 -04:00
Shengchen Kan
f3d9abf1f8 [X86][mem-fold] Use the generated memory folding table
Reviewed By: yubing

Differential Revision: https://reviews.llvm.org/D147527
2023-04-06 19:49:39 +08:00
Shengchen Kan
35aeb321c0 [X86][NFC] Remove redundant flags used in x86-auto-memfold.td 2023-04-04 19:37:28 +08:00