369891b674
In most cases, the type information attached to load and store instructions is meaningless and inconsistently applied. We can usually use ".b" loads and avoid the complexity of trying to assign the correct type. The one expectation is sign-extending load, which will continue to use ".s" to ensure the sign extension into a larger register is done correctly.
246 lines
7.7 KiB
LLVM
246 lines
7.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mcpu=sm_50 | FileCheck %s
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; RUN: %if ptxas %{ llc < %s -mcpu=sm_50 | %ptxas-verify %}
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target triple = "nvptx64-nvidia-cuda"
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define i32 @test_simple_rotl(i32 %x) {
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; CHECK-LABEL: test_simple_rotl(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<3>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [test_simple_rotl_param_0];
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; CHECK-NEXT: shf.l.wrap.b32 %r2, %r1, %r1, 7;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
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; CHECK-NEXT: ret;
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%shl = shl i32 %x, 7
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%shr = lshr i32 %x, 25
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%add = add i32 %shl, %shr
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ret i32 %add
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}
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define i32 @test_simple_rotr(i32 %x) {
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; CHECK-LABEL: test_simple_rotr(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<3>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [test_simple_rotr_param_0];
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; CHECK-NEXT: shf.l.wrap.b32 %r2, %r1, %r1, 25;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
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; CHECK-NEXT: ret;
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%shr = lshr i32 %x, 7
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%shl = shl i32 %x, 25
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%add = add i32 %shr, %shl
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ret i32 %add
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}
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define i32 @test_rotl_var(i32 %x, i32 %y) {
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; CHECK-LABEL: test_rotl_var(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<4>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [test_rotl_var_param_0];
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; CHECK-NEXT: ld.param.b32 %r2, [test_rotl_var_param_1];
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; CHECK-NEXT: shf.l.wrap.b32 %r3, %r1, %r1, %r2;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
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; CHECK-NEXT: ret;
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%shl = shl i32 %x, %y
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%sub = sub i32 32, %y
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%shr = lshr i32 %x, %sub
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%add = add i32 %shl, %shr
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ret i32 %add
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}
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define i32 @test_rotr_var(i32 %x, i32 %y) {
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; CHECK-LABEL: test_rotr_var(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<4>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [test_rotr_var_param_0];
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; CHECK-NEXT: ld.param.b32 %r2, [test_rotr_var_param_1];
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; CHECK-NEXT: shf.r.wrap.b32 %r3, %r1, %r1, %r2;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
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; CHECK-NEXT: ret;
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%shr = lshr i32 %x, %y
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%sub = sub i32 32, %y
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%shl = shl i32 %x, %sub
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%add = add i32 %shr, %shl
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ret i32 %add
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}
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define i32 @test_invalid_rotl_var_and(i32 %x, i32 %y) {
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; CHECK-LABEL: test_invalid_rotl_var_and(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<8>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [test_invalid_rotl_var_and_param_0];
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; CHECK-NEXT: ld.param.b32 %r2, [test_invalid_rotl_var_and_param_1];
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; CHECK-NEXT: shl.b32 %r3, %r1, %r2;
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; CHECK-NEXT: neg.s32 %r4, %r2;
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; CHECK-NEXT: and.b32 %r5, %r4, 31;
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; CHECK-NEXT: shr.u32 %r6, %r1, %r5;
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; CHECK-NEXT: add.s32 %r7, %r6, %r3;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r7;
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; CHECK-NEXT: ret;
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%shr = shl i32 %x, %y
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%sub = sub nsw i32 0, %y
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%and = and i32 %sub, 31
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%shl = lshr i32 %x, %and
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%add = add i32 %shl, %shr
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ret i32 %add
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}
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define i32 @test_invalid_rotr_var_and(i32 %x, i32 %y) {
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; CHECK-LABEL: test_invalid_rotr_var_and(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<8>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [test_invalid_rotr_var_and_param_0];
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; CHECK-NEXT: ld.param.b32 %r2, [test_invalid_rotr_var_and_param_1];
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; CHECK-NEXT: shr.u32 %r3, %r1, %r2;
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; CHECK-NEXT: neg.s32 %r4, %r2;
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; CHECK-NEXT: and.b32 %r5, %r4, 31;
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; CHECK-NEXT: shl.b32 %r6, %r1, %r5;
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; CHECK-NEXT: add.s32 %r7, %r3, %r6;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r7;
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; CHECK-NEXT: ret;
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%shr = lshr i32 %x, %y
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%sub = sub nsw i32 0, %y
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%and = and i32 %sub, 31
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%shl = shl i32 %x, %and
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%add = add i32 %shr, %shl
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ret i32 %add
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}
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define i32 @test_fshl_special_case(i32 %x0, i32 %x1, i32 %y) {
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; CHECK-LABEL: test_fshl_special_case(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<5>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [test_fshl_special_case_param_0];
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; CHECK-NEXT: ld.param.b32 %r2, [test_fshl_special_case_param_1];
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; CHECK-NEXT: ld.param.b32 %r3, [test_fshl_special_case_param_2];
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; CHECK-NEXT: shf.l.wrap.b32 %r4, %r2, %r1, %r3;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
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; CHECK-NEXT: ret;
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%shl = shl i32 %x0, %y
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%srli = lshr i32 %x1, 1
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%x = xor i32 %y, 31
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%srlo = lshr i32 %srli, %x
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%o = add i32 %shl, %srlo
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ret i32 %o
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}
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define i32 @test_fshr_special_case(i32 %x0, i32 %x1, i32 %y) {
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; CHECK-LABEL: test_fshr_special_case(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<5>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [test_fshr_special_case_param_0];
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; CHECK-NEXT: ld.param.b32 %r2, [test_fshr_special_case_param_1];
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; CHECK-NEXT: ld.param.b32 %r3, [test_fshr_special_case_param_2];
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; CHECK-NEXT: shf.r.wrap.b32 %r4, %r2, %r1, %r3;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
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; CHECK-NEXT: ret;
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%shl = lshr i32 %x1, %y
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%srli = shl i32 %x0, 1
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%x = xor i32 %y, 31
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%srlo = shl i32 %srli, %x
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%o = add i32 %shl, %srlo
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ret i32 %o
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}
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define i64 @test_rotl_udiv_special_case(i64 %i) {
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; CHECK-LABEL: test_rotl_udiv_special_case(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<5>;
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; CHECK-NEXT: .reg .b64 %rd<5>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b64 %rd1, [test_rotl_udiv_special_case_param_0];
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; CHECK-NEXT: mul.hi.u64 %rd2, %rd1, -6148914691236517205;
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; CHECK-NEXT: shr.u64 %rd3, %rd2, 1;
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; CHECK-NEXT: mov.b64 {%r1, %r2}, %rd3;
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; CHECK-NEXT: shf.l.wrap.b32 %r3, %r2, %r1, 28;
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; CHECK-NEXT: shf.l.wrap.b32 %r4, %r1, %r2, 28;
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; CHECK-NEXT: mov.b64 %rd4, {%r4, %r3};
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; CHECK-NEXT: st.param.b64 [func_retval0], %rd4;
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; CHECK-NEXT: ret;
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%lhs_div = udiv i64 %i, 3
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%rhs_div = udiv i64 %i, 48
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%lhs_shift = shl i64 %lhs_div, 60
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%out = add i64 %lhs_shift, %rhs_div
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ret i64 %out
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}
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define i32 @test_rotl_mul_special_case(i32 %i) {
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; CHECK-LABEL: test_rotl_mul_special_case(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<4>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [test_rotl_mul_special_case_param_0];
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; CHECK-NEXT: mul.lo.s32 %r2, %r1, 9;
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; CHECK-NEXT: shf.l.wrap.b32 %r3, %r2, %r2, 7;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
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; CHECK-NEXT: ret;
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%lhs_mul = mul i32 %i, 9
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%rhs_mul = mul i32 %i, 1152
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%lhs_shift = lshr i32 %lhs_mul, 25
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%out = add i32 %lhs_shift, %rhs_mul
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ret i32 %out
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}
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define i64 @test_rotl_mul_with_mask_special_case(i64 %i) {
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; CHECK-LABEL: test_rotl_mul_with_mask_special_case(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<7>;
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; CHECK-NEXT: .reg .b64 %rd<5>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b64 %rd1, [test_rotl_mul_with_mask_special_case_param_0];
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; CHECK-NEXT: mul.lo.s64 %rd2, %rd1, 9;
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; CHECK-NEXT: mov.b64 {%r1, %r2}, %rd1;
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; CHECK-NEXT: mov.b64 {%r3, %r4}, %rd2;
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; CHECK-NEXT: shf.l.wrap.b32 %r5, %r4, %r1, 7;
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; CHECK-NEXT: shf.l.wrap.b32 %r6, %r1, %r2, 7;
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; CHECK-NEXT: mov.b64 %rd3, {%r5, %r6};
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; CHECK-NEXT: and.b64 %rd4, %rd3, 255;
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; CHECK-NEXT: st.param.b64 [func_retval0], %rd4;
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; CHECK-NEXT: ret;
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%lhs_mul = mul i64 %i, 1152
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%rhs_mul = mul i64 %i, 9
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%lhs_and = and i64 %lhs_mul, 160
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%rhs_shift = lshr i64 %rhs_mul, 57
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%out = add i64 %lhs_and, %rhs_shift
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ret i64 %out
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}
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define i32 @test_fshl_with_mask_special_case(i32 %x) {
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; CHECK-LABEL: test_fshl_with_mask_special_case(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<5>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [test_fshl_with_mask_special_case_param_0];
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; CHECK-NEXT: or.b32 %r2, %r1, 1;
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; CHECK-NEXT: shf.l.wrap.b32 %r3, %r1, %r2, 5;
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; CHECK-NEXT: and.b32 %r4, %r3, -31;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
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; CHECK-NEXT: ret;
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%or1 = or i32 %x, 1
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%sh1 = shl i32 %or1, 5
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%sh2 = lshr i32 %x, 27
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%1 = and i32 %sh2, 1
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%r = add i32 %sh1, %1
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ret i32 %r
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}
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