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paperchalice 945a186089
[DAGCombiner] Remove most UnsafeFPMath references (#146295) 
This pull request removes all references to `UnsafeFPMath` in dag
combiner except FP_ROUND.
- Set fast math flags in some tests.
2025-08-22 15:27:25 +08:00
..
access-non-generic.ll
[NVPTX] Allow directly storing immediates to improve readability (#145552)
2025-06-25 18:46:39 -07:00
activemask.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
add-sub-128bit.ll
[NVPTX] Cleanup ISel for selp.* (#135065)
2025-04-09 14:21:12 -07:00
addr-mode.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
addrspacecast-cse.ll
[SDAG] Fix CSE for ADDRSPACECAST nodes (#122912)
2025-01-20 09:09:22 -08:00
addrspacecast-folding.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
addrspacecast-gvar.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
addrspacecast-ptx64.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
addrspacecast.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
aggr-param.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
aggregate-return.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
alias-errors.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
alias.ll
[NVPTX] Consolidate and cleanup various NVPTXISD nodes (NFC) (#145581)
2025-06-25 11:42:21 -07:00
and-or-setcc.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
annotations.ll
[NVPTX] Convert vector function nvvm.annotations to attributes (#127736)
2025-02-26 08:45:27 -08:00
anonymous-fn-param.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
APIntLoadStore.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
APIntParam.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
APIntSextParam.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
APIntZextParam.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
applypriority.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
arg-lowering.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
arithmetic-fp-sm20.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
arithmetic-int.ll
[NVPTX] Add some more immediate instruction variants (#122746)
2025-01-14 21:28:29 -08:00
async-copy.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
atomic-lower-local.ll
…
atomicrmw-expand.err.ll
AtomicExpand: Stop using report_fatal_error (#147300)
2025-07-09 15:28:10 +09:00
atomicrmw-expand.ll
[NVPTX] Add syncscope support for cmpxchg (#140812)
2025-07-15 17:08:52 -07:00
atomics-sm60.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
atomics-sm70.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
atomics-sm90.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
atomics-with-scope.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
atomics.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
b52037.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
barrier.ll
Reland "[NVPTX] Unify and extend barrier{.cta} intrinsic support" (#141143)
2025-05-22 19:38:10 -07:00
bf16-instructions.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
bf16.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
bf16x2-instructions-approx.ll
[NVPTX] Remove UnsafeFPMath uses (#151479)
2025-08-14 08:42:29 +08:00
bf16x2-instructions.ll
[NVPTX] Legalize aext-load to zext-load to expose more DAG combines (#154251)
2025-08-21 15:33:23 -07:00
bfe.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
blocksareclusters-kernel-attr.ll
[NVPTX] Add support for "blocksareclusters" kernel attr (#152265)
2025-08-20 11:09:39 +05:30
bmsk.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
boolean-patterns.ll
[DAG] getNode - convert scalar i1 arithmetic calls to bitwise instructions (#125486)
2025-02-03 16:36:01 +00:00
branch-fold.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
branch-fold.mir
[NVPTX] miscellaneous minor cleanup (NFC) (#152329)
2025-08-12 18:15:01 -07:00
brkpt.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
bswap.ll
[NVPTX] Add intrinsic support for specialized prmt variants (#140951)
2025-05-22 13:05:17 -07:00
bug17709.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
bug21465.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
bug22246.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
bug22322.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
bug26185-2.ll
[NVPTX] Enhance mul.wide and mad.wide peepholes (#150477)
2025-07-30 08:57:19 -07:00
bug26185.ll
[NVPTX] Cleanup ld/st lowering (#143936)
2025-06-17 09:00:18 -07:00
bug41651.ll
…
bug52623.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
bypass-div.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
byval-arg-vectorize.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
byval-const-global.ll
[NVPTX] Fix v2i8 call lowering, use generic ld/st nodes for call params (#146930)
2025-07-28 10:41:51 -07:00
call_bitcast_byval.ll
[NVPTX] Fix v2i8 call lowering, use generic ld/st nodes for call params (#146930)
2025-07-28 10:41:51 -07:00
call-with-alloca-buffer.ll
[NVPTX] Fix v2i8 call lowering, use generic ld/st nodes for call params (#146930)
2025-07-28 10:41:51 -07:00
callchain.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
calling-conv.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
calls-with-phi.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
chain-different-as.ll
[NVPTX] Allow directly storing immediates to improve readability (#145552)
2025-06-25 18:46:39 -07:00
cluster-dim.ll
[NVPTX] Convert vector function nvvm.annotations to attributes (#127736)
2025-02-26 08:45:27 -08:00
clusterlaunchcontrol-multicast.ll
[LLVM][NVPTX] Add NVPTX codegen support for clusterlaunchcontrol instruction (#134568)
2025-05-20 16:05:10 +05:30
clusterlaunchcontrol.ll
[LLVM][NVPTX] Add NVPTX codegen support for clusterlaunchcontrol instruction (#134568)
2025-05-20 16:05:10 +05:30
cmpxchg-sm60.ll
[NVPTX] Legalize aext-load to zext-load to expose more DAG combines (#154251)
2025-08-21 15:33:23 -07:00
cmpxchg-sm70.ll
[NVPTX] Legalize aext-load to zext-load to expose more DAG combines (#154251)
2025-08-21 15:33:23 -07:00
cmpxchg-sm90.ll
[NVPTX] Legalize aext-load to zext-load to expose more DAG combines (#154251)
2025-08-21 15:33:23 -07:00
cmpxchg.ll
[NVPTX] Legalize aext-load to zext-load to expose more DAG combines (#154251)
2025-08-21 15:33:23 -07:00
cmpxchg.py
[NVPTX] Add syncscope support for cmpxchg (#140812)
2025-07-15 17:08:52 -07:00
combine-mad.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
combine-min-max.ll
[NVPTX] Fix ptxas-verify line.
2025-08-05 12:03:11 +00:00
combine-wide.ll
[NVPTX] Enhance mul.wide and mad.wide peepholes (#150477)
2025-07-30 08:57:19 -07:00
common-linkage.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
compare-int.ll
[NVPTX] Fix v2i8 call lowering, use generic ld/st nodes for call params (#146930)
2025-07-28 10:41:51 -07:00
compute-ptx-value-vts.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
constant-vectors.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
convergent-mir-call.ll
[NVPTX] Consolidate and cleanup various NVPTXISD nodes (NFC) (#145581)
2025-06-25 11:42:21 -07:00
convert-call-to-indirect.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
convert-fp-i8.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
convert-fp.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
convert-int-sm20.ll
[NVPTX] Further cleanup call isel (#146411)
2025-07-01 14:55:04 -07:00
convert-sm80.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
convert-sm89.ll
[NVPTX] Add float to tf32 conversion intrinsics (#121507)
2025-01-13 16:17:42 +05:30
convert-sm90.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
convert-sm100.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
convert-sm100a.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
copysign.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
cp-async-bulk-s2g-sm100.ll
[NVPTX] Add TMA Bulk Copy Intrinsics (#138679)
2025-05-15 16:08:01 +05:30
cp-async-bulk-tensor-g2s-1cta.ll
[NVPTX] Add cta_group support to TMA G2S intrinsics (#143178)
2025-06-12 15:20:39 +05:30
cp-async-bulk-tensor-g2s-2cta.ll
[NVPTX] Add cta_group support to TMA G2S intrinsics (#143178)
2025-06-12 15:20:39 +05:30
cp-async-bulk-tensor-g2s-cta-sm90.ll
[NVPTX] Add im2colw/w128 modes support to TMA intrinsics (#148863)
2025-07-19 17:16:21 +05:30
cp-async-bulk-tensor-g2s-cta-sm100.ll
[NVPTX] Add im2colw/w128 modes support to TMA intrinsics (#148863)
2025-07-19 17:16:21 +05:30
cp-async-bulk-tensor-g2s-cta-sm100a.ll
[NVPTX] Add im2colw/w128 modes support to TMA intrinsics (#148863)
2025-07-19 17:16:21 +05:30
cp-async-bulk-tensor-g2s-gather4.ll
[NVPTX] Add im2colw/w128 modes support to TMA intrinsics (#148863)
2025-07-19 17:16:21 +05:30
cp-async-bulk-tensor-g2s-im2colw128.ll
[NVPTX] Add im2colw/w128 modes support to TMA intrinsics (#148863)
2025-07-19 17:16:21 +05:30
cp-async-bulk-tensor-g2s-im2colw.ll
[NVPTX] Add im2colw/w128 modes support to TMA intrinsics (#148863)
2025-07-19 17:16:21 +05:30
cp-async-bulk-tensor-g2s-invalid.ll
[NVPTX] Add cta_group support to TMA G2S intrinsics (#143178)
2025-06-12 15:20:39 +05:30
cp-async-bulk-tensor-g2s.ll
[NVPTX][Tests-only] Update TMA intrinsic tests (#147364)
2025-07-08 21:38:44 +05:30
cp-async-bulk-tensor-prefetch-sm100a.ll
[NVPTX] Add im2colw/w128 modes support to TMA intrinsics (#148863)
2025-07-19 17:16:21 +05:30
cp-async-bulk-tensor-prefetch.ll
[NVPTX][NFC] Move more TMA intrinsics lowering to tablegen (#147576)
2025-07-11 12:33:46 +05:30
cp-async-bulk-tensor-reduce.ll
[NVPTX][Tests-only] Update TMA intrinsic tests (#147364)
2025-07-08 21:38:44 +05:30
cp-async-bulk-tensor-s2g-scatter4.ll
[NVPTX] Add im2colw/w128 modes support to TMA intrinsics (#148863)
2025-07-19 17:16:21 +05:30
cp-async-bulk-tensor-s2g.ll
[NVPTX][NFC] Move more TMA intrinsics lowering to tablegen (#147576)
2025-07-11 12:33:46 +05:30
cp-async-bulk.ll
[NVPTX][NFC] Move more TMA lowering to tablegen (#140914)
2025-05-29 12:46:01 +05:30
cse-mov-sym.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
ctlz.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
ctpop.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
cttz.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
dag-cse.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
demote-vars.ll
[NVPTX] Allow directly storing immediates to improve readability (#145552)
2025-06-25 18:46:39 -07:00
disable-opt.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
discard.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
disjoint-or-addr.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
distributed-shared-cluster.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
div-ri.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
div.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
divrem-combine.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
dot-product.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
dynamic_stackalloc.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
dynamic-stackalloc-regression.ll
[NVPTX] Fixup under-aligned dynamic alloca lowering (#139628)
2025-05-13 09:56:41 -07:00
elect.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
empty-type.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
envreg.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
extloadv.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
extractelement.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
f16-abs.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
f16-ex2.ll
[NVPTX] Improve support for {ex2,lg2}.approx (#120519)
2025-01-16 12:21:32 -08:00
f16-instructions.ll
[NVPTX] Remove UnsafeFPMath uses (#151479)
2025-08-14 08:42:29 +08:00
f16x2-instructions.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
f32-ex2.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
f32-lg2.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
f32x2-instructions.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
fabs-intrinsics.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
fast-math.ll
[NVPTX] Remove UnsafeFPMath uses (#151479)
2025-08-14 08:42:29 +08:00
fcos-no-fast-math.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
fence-cluster.ll
[NVPTX] fix ptxas tests introduced by #124865 (#125927)
2025-02-05 15:47:05 -08:00
fence-nocluster.ll
[NVPTX] fix ptxas tests introduced by #124865 (#125927)
2025-02-05 15:47:05 -08:00
fence-proxy-tensormap.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
fence.py
[NVPTX] Support for fence.acquire and fence.release (#124865)
2025-02-04 14:20:00 -08:00
fexp2.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
filetype-null.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
flo.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
flog2.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
fma-assoc.ll
[DAGCombiner] Remove most UnsafeFPMath references (#146295)
2025-08-22 15:27:25 +08:00
fma-disable.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
fma-relu-contract.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
fma-relu-fma-intrinsic.ll
[NVPTX] Remove UnsafeFPMath uses (#151479)
2025-08-14 08:42:29 +08:00
fma-relu-instruction-flag.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
fma.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
fminimum-fmaximum.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
fns.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
fold-movs.ll
[NVPTX] fix type propagation when expanding Store[V4 -> V8] (#151576)
2025-07-31 16:52:42 -07:00
forward-ld-param.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
fp16.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
fp128-storage-type.ll
[NVPTX] Consolidate and cleanup various NVPTXISD nodes (NFC) (#145581)
2025-06-25 11:42:21 -07:00
fp-contract-f32x2.ll
[NVPTX] support f32x2 instructions for sm_100+ (#126337)
2025-07-11 11:50:50 -07:00
fp-contract.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
fp-literals.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
frameindex-lifetime.ll
[IR] Remove size argument from lifetime intrinsics (#150248)
2025-08-08 11:09:34 +02:00
frem.ll
[NVPTX] Remove UnsafeFPMath uses (#151479)
2025-08-14 08:42:29 +08:00
fsin-no-fast-math.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
function-align.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
funnel-shift-clamp.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
generic-to-nvvm-ir.ll
…
generic-to-nvvm.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
global-addrspace.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
global-ctor-empty.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
global-incomplete-init.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
global-ordering.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
global-variable-big.ll
[NVPTX] Basic support for fp128 as a storage type (#136006)
2025-04-17 13:19:48 -07:00
global-visibility.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
globals_init.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
globals_lowering.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
griddepcontrol.ll
[NVPTX] Fix ptxas failures (NFC) (#125147)
2025-02-01 16:44:37 -08:00
gvar-init.ll
[NVPTX][test] Use 'not' to switch an XFAIL test to PASS (#130839)
2025-03-12 09:20:48 -07:00
half.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
i1-array-global.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
i1-ext-load.ll
[NVPTX] Cleanup ld/st lowering (#143936)
2025-06-17 09:00:18 -07:00
i1-global.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
i1-icmp.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
i1-int-to-fp.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
i1-load-lower.ll
[NVPTX] Allow directly storing immediates to improve readability (#145552)
2025-06-25 18:46:39 -07:00
i1-param.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
i1-select.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
i8-param.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
i8x2-instructions.ll
[NVPTX] Implement computeKnownBitsForTargetNode for LoadV (#154165)
2025-08-20 18:57:15 +00:00
i8x4-instructions.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
i16x2-instructions.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
i128-array.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
i128-global.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
i128-ld-st.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
i128-param.ll
[NVPTX] Fix v2i8 call lowering, use generic ld/st nodes for call params (#146930)
2025-07-28 10:41:51 -07:00
i128-retval.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
i128-struct.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
i128.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
idioms.ll
[NVPTX] Fix v2i8 call lowering, use generic ld/st nodes for call params (#146930)
2025-07-28 10:41:51 -07:00
imad.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
indirect_byval.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
inline-asm-b128-test1.ll
[NVPTX] Rework and cleanup FTZ ISel (#146410)
2025-07-09 11:16:48 -07:00
inline-asm-b128-test2.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
inline-asm-b128-test3.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
inline-asm.ll
[NVPTX] Cleanup ISel code after float register removal, use BasicNVPTXInst (#141711)
2025-05-29 12:24:31 -07:00
inlineasm-output-template.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
intr-range.ll
[NVPTX] Add ranges to intrinsic definitions, cleanup NVVMIntrRange (#138338)
2025-05-05 16:22:25 -07:00
intrinsic-old.ll
[NVPTX] Add ranges to intrinsic definitions, cleanup NVVMIntrRange (#138338)
2025-05-05 16:22:25 -07:00
intrinsics-sm90.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
intrinsics.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
isspacep.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
jump-table.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
kernel-param-align.ll
[NVPTX] Fix ptxas failures (NFC) (#125147)
2025-02-01 16:44:37 -08:00
ld-addrspace.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
ld-generic.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
ld-param-sink.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
ld-st-addrrspace.py
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
ldg-invariant-256.ll
[NVPTX] Use PRMT more widely, and improve folding around this instruction (#148261)
2025-07-13 15:06:53 -07:00
ldg-invariant.ll
[NVPTX] Use PRMT more widely, and improve folding around this instruction (#148261)
2025-07-13 15:06:53 -07:00
ldparam-v4.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
ldu-i8.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
ldu-ldg.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
ldu-reg-plus-offset.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
lit.local.cfg
[NVPTX] Support for memory orderings for cmpxchg (#126159)
2025-02-24 10:13:23 -08:00
load-sext-i1.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
load-store-256-addressing-invariant.ll
[NVPTX] support f32x2 instructions for sm_100+ (#126337)
2025-07-11 11:50:50 -07:00
load-store-256-addressing.ll
[NVPTX] support f32x2 instructions for sm_100+ (#126337)
2025-07-11 11:50:50 -07:00
load-store-scalars.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
load-store-sm-70.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
load-store-sm-90.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
load-store-vectors-256.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
load-store-vectors.ll
[NVPTX] Use PRMT more widely, and improve folding around this instruction (#148261)
2025-07-13 15:06:53 -07:00
load-with-non-coherent-cache.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
LoadStoreVectorizer.ll
[NVPTX] Add SimplifyDemandedBitsForTargetNode for PRMT (#149395)
2025-07-22 18:44:50 -07:00
local-stack-frame.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
loop-vectorize.ll
…
lower-aggr-copies.ll
[NVPTX] Rework and cleanup FTZ ISel (#146410)
2025-07-09 11:16:48 -07:00
lower-alloca.ll
[NVPTX] Allow directly storing immediates to improve readability (#145552)
2025-06-25 18:46:39 -07:00
lower-args-alignment.ll
[NVPTXLowerArgs] Add align attribute to return value of addrspace.wrap intrinsic (#153889)
2025-08-19 11:13:57 -05:00
lower-args-gridconstant.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
lower-args.ll
[NVPTXLowerArgs] Add align attribute to return value of addrspace.wrap intrinsic (#153889)
2025-08-19 11:13:57 -05:00
lower-byval-args.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
lower-ctor-dtor.ll
[NVPTX] Convert vector function nvvm.annotations to attributes (#127736)
2025-02-26 08:45:27 -08:00
lower-kernel-ptr-arg.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
machine-sink.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
MachineSink-call.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
MachineSink-convergent.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
managed.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
match.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
math-intrins-sm53-ptx42.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
math-intrins-sm80-ptx70-autoupgrade.ll
[NVPTX] Cleanup and document nvvm.fabs intrinsics, adding f16 support (#135644)
2025-04-17 07:37:24 -07:00
math-intrins-sm80-ptx70-instcombine.ll
…
math-intrins-sm80-ptx70.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
math-intrins-sm86-ptx72-autoupgrade.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
math-intrins-sm86-ptx72.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
math-intrins.ll
[NVPTX] Rework and cleanup FTZ ISel (#146410)
2025-07-09 11:16:48 -07:00
max-align.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
maxclusterrank.ll
[NVPTX] Convert vector function nvvm.annotations to attributes (#127736)
2025-02-26 08:45:27 -08:00
mbarrier.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
minmax-negative.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
misaligned-vector-ldst.ll
[NVPTX] Legalize aext-load to zext-load to expose more DAG combines (#154251)
2025-08-21 15:33:23 -07:00
misched_func_call.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
mma-no-sink-after-laneid-check.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
module-inline-asm.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
mulhi-intrins.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
mulwide.ll
[NVPTX] Legalize aext-load to zext-load to expose more DAG combines (#154251)
2025-08-21 15:33:23 -07:00
naked-fn-with-frame-pointer.ll
[NVPTX] Consolidate and cleanup various NVPTXISD nodes (NFC) (#145581)
2025-06-25 11:42:21 -07:00
nanosleep.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
no-extra-parens.ll
[NVPTX] cleanup & canonicalize mov (#129344)
2025-03-23 14:53:00 -07:00
no-f32x2.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
no-stack-protector-libcall-error.ll
StackProtector: Use RuntimeLibcalls to query libcall names (#147913)
2025-07-15 18:37:59 +09:00
noduplicate-syncthreads.ll
Reland "[NVPTX] Unify and extend barrier{.cta} intrinsic support" (#141143)
2025-05-22 19:38:10 -07:00
nofunc.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
noreturn.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
nounroll.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
nvcl-param-align.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
nvptx-aa-inline-asm.ll
[NVPTX] Improve modeling of inline PTX (#130675)
2025-03-25 13:46:16 -07:00
nvptx-aa.ll
[NVPTX] Add support for Shared Cluster Memory address space [1/2] (#135444)
2025-04-22 15:14:39 -07:00
nvptx-prec-divf32-flag.ll
[NVPTX] Add -nvptx-prec-divf32=3 to disable ftz for f32 fdiv (#141276)
2025-05-27 13:55:20 -07:00
NVPTXAA_before_BasicAA.ll
[NVPTX] Fix NVPTXAA_before_BasicAA Test (#138992)
2025-05-07 16:59:33 -07:00
nvvm-annotations-D120129.ll
…
nvvm-reflect-arch-O0.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
nvvm-reflect-arch.ll
[NVPTX] Fix failing test and incorrect mcpu reading in reflect
2025-01-21 13:25:04 -06:00
nvvm-reflect-module-flag.ll
…
nvvm-reflect-ocl.ll
[NVPTX] Fix failing test and incorrect mcpu reading in reflect
2025-01-21 13:25:04 -06:00
nvvm-reflect-opaque.ll
[NVPTX] Do not run the NVVMReflect pass as part of the normal pipeline (#121834)
2025-01-07 14:45:03 -06:00
nvvm-reflect-options.ll
[NVPTX] Improve NVVMReflect Efficiency (#134416)
2025-04-10 18:33:37 -07:00
nvvm-reflect.ll
[NVPTX] Do not run the NVVMReflect pass as part of the normal pipeline (#121834)
2025-01-07 14:45:03 -06:00
packed-aggr.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
param-add.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
param-align.ll
[NVPTX] Allow directly storing immediates to improve readability (#145552)
2025-06-25 18:46:39 -07:00
param-load-store.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
param-overalign.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
param-vectorize-device.ll
[NVPTX] Vectorize loads when lowering of byval calls, misc. cleanup (#151070)
2025-08-01 15:02:02 -07:00
param-vectorize-kernel.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
pass-name.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
pm-event.ll
[NVPTX] Add pm_event intrinsics (#141278)
2025-06-06 19:39:33 +05:30
pow2_mask_cmp.ll
[NVPTX] Further cleanup call isel (#146411)
2025-07-01 14:55:04 -07:00
pr13291-i1-store.ll
[NVPTX] Allow directly storing immediates to improve readability (#145552)
2025-06-25 18:46:39 -07:00
pr16278.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
pr17529.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
pr126337.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
prefetch-inferas-test.ll
[NVPTX][Test-only] Add proper sm-version to ptxas-verify in prefetch-inferas-test.ll (#152492)
2025-08-07 22:42:00 +05:30
prefetch.ll
[NVPTX] Add prefetch tensormap variant (#146203)
2025-08-07 16:19:21 +05:30
prmt-const-folding.ll
[NVPTX] Add PRMT constant folding and cleanup usage of PRMT node (#148906)
2025-07-17 11:10:23 -07:00
prmt.ll
[NVPTX] Use prmt.f4e to lower pointer alignment fshr idiom (#143407)
2025-06-12 23:09:55 -07:00
proxy-reg-erasure-ptx.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
proxy-reg-erasure.mir
[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)
2025-08-12 11:23:05 -07:00
rcp-opt.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
read-global-variable-constant.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
reduction-intrinsics.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
redux-sync-f32.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
redux-sync.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
refl1.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
reg-copy.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
reg-types.ll
[NVPTX] Allow directly storing immediates to improve readability (#145552)
2025-06-25 18:46:39 -07:00
rotate_64.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
rotate-add.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
rotate.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
rsqrt-opt.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
rsqrt.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
sad-intrins.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
sched1.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
sched2.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
setmaxnreg-sm100a.ll
[NVPTX] Update setmaxnreg intrinsic lowering (#125846)
2025-02-06 15:23:55 +00:00
setmaxnreg.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
sext-in-reg.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
sext-params.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
sext-setcc.ll
[DAGCombiner] Fold setcc of trunc, generalizing some NVPTX isel logic (#150270)
2025-08-05 19:20:17 -07:00
shfl-p.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
shfl-sync-p.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
shfl-sync.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
shfl.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
shift-opt.ll
[NVPTX] Implement computeKnownBitsForTargetNode for LoadV (#154165)
2025-08-20 18:57:15 +00:00
shift-parts.ll
[NVPTX] Add some more immediate instruction variants (#122746)
2025-01-14 21:28:29 -08:00
short-ptr.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
shuffle-vec-undef-init.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
simple-call.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
sm-version.ll
[NVPTX] Add family-specific architectures support (#141899)
2025-06-19 12:18:17 +05:30
speculative-execution-divergent-target.ll
…
sqrt-approx.ll
[NVPTX] Remove UnsafeFPMath uses (#151479)
2025-08-14 08:42:29 +08:00
st_bulk.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
st-addrspace.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
st-generic.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
st-param-imm.ll
[NVPTX] Fix v2i8 call lowering, use generic ld/st nodes for call params (#146930)
2025-07-28 10:41:51 -07:00
stacksaverestore.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
store-retval.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
store-undef.ll
[NVPTX] Fix v2i8 call lowering, use generic ld/st nodes for call params (#146930)
2025-07-28 10:41:51 -07:00
surf-read-cuda.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
surf-read.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
surf-tex.py
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
surf-write-cuda.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
surf-write.ll
Reland "[NVPTX] Cleanup/Refactoring in NVPTX AsmPrinter and RegisterInfo (NFC)" (#127277)
2025-02-14 18:45:14 -08:00
symbol-naming.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
szext.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
tag-invariant-loads.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
TailDuplication-convergent.ll
…
tanhf.ll
[LLVM][NVPTX] Upstream tanh intrinsic for libdevice (#149596)
2025-07-24 14:32:59 -07:00
tcgen05-alloc.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
tcgen05-commit.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
tcgen05-cp.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
tcgen05-fence.ll
[NVPTX] Add tcgen05 wait/fence/commit intrinsics (#126091)
2025-02-07 22:10:25 +05:30
tcgen05-ld.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
tcgen05-shift.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
tcgen05-st.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
tex-read-cuda.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
tex-read.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
texsurf-queries.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
tid-range.ll
[NVPTX] Rework and cleanup FTZ ISel (#146410)
2025-07-09 11:16:48 -07:00
trunc-setcc.ll
[DAGCombiner] Fold setcc of trunc, generalizing some NVPTX isel logic (#150270)
2025-08-05 19:20:17 -07:00
trunc-tofp.ll
[NVPTX][test] fixup version for ptxas on trunc-tofp.ll (#149558)
2025-07-18 13:27:31 -07:00
unaligned-param-load-store.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
unfold-masked-merge-vector-variablemask.ll
[NVPTX] fold movs into loads and stores (#144581)
2025-06-24 16:02:13 -04:00
unreachable.ll
[NVPTX] Consolidate and cleanup various NVPTXISD nodes (NFC) (#145581)
2025-06-25 11:42:21 -07:00
unrecognized-sm1x.ll
[NVPTX] Require asserts in unrecognized-sm1x.ll (#126105)
2025-02-06 11:17:55 -08:00
upgrade-nvvm-annotations.ll
[NVPTX] Auto-Upgrade !"align" metadata on return values to stackalign (#131726)
2025-03-24 12:00:44 -07:00
vaargs.ll
[NVPTX] Fix v2i8 call lowering, use generic ld/st nodes for call params (#146930)
2025-07-28 10:41:51 -07:00
variadics-backend.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
variadics-lowering.ll
[IR] Remove size argument from lifetime intrinsics (#150248)
2025-08-08 11:09:34 +02:00
vec8.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
vec-param-load.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
vector-args.ll
[NVPTX] support f32x2 instructions for sm_100+ (#126337)
2025-07-11 11:50:50 -07:00
vector-call.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
vector-compare.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
vector-global.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
vector-loads.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
vector-returns.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
vector-select.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
vector-stores.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
vectorize-misaligned.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
vote.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
weak-global.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
weak-linkage.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
wgmma-sm90a-fence.ll
[NVPTX] Add intrinsics for wgmma.fence PTX instructions (#120523)
2024-12-20 15:25:06 -05:00
wmma-ptx60-sm70.py
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
wmma-ptx61-sm70.py
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
wmma-ptx63-sm72.py
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
wmma-ptx63-sm75.py
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
wmma-ptx64-sm70.py
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
wmma-ptx65-sm75.py
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
wmma-ptx71-sm80.py
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
wmma-ptx78-sm90.py
[NVPTX] Lower stmatrix intrinsics to PTX (#148561)
2025-07-20 21:06:45 -07:00
wmma-ptx86-sm100a.py
[NVPTX] Lower stmatrix intrinsics to PTX (#148561)
2025-07-20 21:06:45 -07:00
wmma-ptx86-sm101a.py
[NVPTX] Lower stmatrix intrinsics to PTX (#148561)
2025-07-20 21:06:45 -07:00
wmma-ptx86-sm120a.py
[NVPTX] Lower stmatrix intrinsics to PTX (#148561)
2025-07-20 21:06:45 -07:00
wmma.py
[NVPTX] Lower stmatrix intrinsics to PTX (#148561)
2025-07-20 21:06:45 -07:00
zeroext-32bit.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00